[PATCH 2/3] drm/i915: Split uncore init into vfunc setup and mmio setup
Chris Wilson
chris at chris-wilson.co.uk
Thu Oct 12 09:00:22 UTC 2017
Some early initialisation functions (like intel_uc_init_early) would
like to access the table of mmio registers sorted by their powerwell,
which is currently setup later in intel_uncore_init(). Since this is a
static table that now doesn't touch hw, once upon a time we needed to
probe ivb to determine the forcewake register, but now only depends on
pciid (i.e. gen) we can do the vfunc setup inside init_early, leaving
the mmio setup where it is.
v2: Split fw_domains_init into early/mmio.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 10 +++--
drivers/gpu/drm/i915/intel_uncore.c | 75 ++++++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_uncore.h | 3 +-
3 files changed, 52 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3db5851756f0..f1eb8df0f3c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -899,13 +899,15 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
- intel_uc_init_early(dev_priv);
- i915_memcpy_init_early(dev_priv);
-
ret = i915_workqueues_init(dev_priv);
if (ret < 0)
goto err_engines;
+ i915_memcpy_init_early(dev_priv);
+
+ intel_uncore_init_early(dev_priv);
+ intel_uc_init_early(dev_priv);
+
/* This must be called before any calls to HAS_PCH_* */
intel_detect_pch(dev_priv);
@@ -1015,7 +1017,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
if (ret < 0)
goto err_bridge;
- intel_uncore_init(dev_priv);
+ intel_uncore_init_mmio(dev_priv);
intel_uc_init_mmio(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 983617b5b338..efe4087dc644 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1125,7 +1125,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
fw_domain_reset(dev_priv, d);
}
-static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
+static void intel_uncore_fw_domains_init_early(struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
return;
@@ -1165,23 +1165,40 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
- } else if (IS_IVYBRIDGE(dev_priv)) {
- u32 ecobus;
+ } else {
+ /*
+ * IVB configs may use multi-threaded forcewake, but
+ * only if the BIOS has configured it. It is too early
+ * too detect the settings here, so we defer that until
+ * intel_uncore_fw_domains_init_mmio().
+ */
+ dev_priv->uncore.funcs.force_wake_get =
+ fw_domains_get_with_thread_status;
+ dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
+ fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+ FORCEWAKE, FORCEWAKE_ACK);
+ }
- /* IVB configs may use multi-threaded forcewake */
+ /* All future platforms are expected to require complex power gating */
+ WARN_ON(dev_priv->uncore.fw_domains == 0);
+}
- /* A small trick here - if the bios hasn't configured
+static void intel_uncore_fw_domains_init_mmio(struct drm_i915_private *dev_priv)
+{
+ if (IS_IVYBRIDGE(dev_priv)) {
+ u32 ecobus;
+
+ /*
+ * IVB configs may use multi-threaded forcewake, part 2
+ *
+ * A small trick here - if the bios hasn't configured
* MT forcewake, and if the device is in RC6, then
* force_wake_mt_get will not wake the device and the
* ECOBUS read will return zero. Which will be
* (correctly) interpreted by the test below as MT
* forcewake being disabled.
- */
- dev_priv->uncore.funcs.force_wake_get =
- fw_domains_get_with_thread_status;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
-
- /* We need to init first for ECOBUS access and then
+ *
+ * We need to init first for ECOBUS access and then
* determine later if we want to reinit, in case of MT access is
* not working. In this stage we don't know which flavour this
* ivb is, so it is better to reset also the gen6 fw registers
@@ -1206,16 +1223,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE, FORCEWAKE_ACK);
}
- } else if (IS_GEN6(dev_priv)) {
- dev_priv->uncore.funcs.force_wake_get =
- fw_domains_get_with_thread_status;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
- fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
- FORCEWAKE, FORCEWAKE_ACK);
}
-
- /* All future platforms are expected to require complex power gating */
- WARN_ON(dev_priv->uncore.fw_domains == 0);
}
#define ASSIGN_FW_DOMAINS_TABLE(d) \
@@ -1251,18 +1259,8 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
return NOTIFY_OK;
}
-void intel_uncore_init(struct drm_i915_private *dev_priv)
+void intel_uncore_init_early(struct drm_i915_private *dev_priv)
{
- i915_check_vgpu(dev_priv);
-
- intel_uncore_edram_detect(dev_priv);
- intel_uncore_fw_domains_init(dev_priv);
- __intel_uncore_early_sanitize(dev_priv, false);
-
- dev_priv->uncore.unclaimed_mmio_check = 1;
- dev_priv->uncore.pmic_bus_access_nb.notifier_call =
- i915_pmic_bus_access_notifier;
-
if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
@@ -1294,6 +1292,21 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
}
+ intel_uncore_fw_domains_init_early(dev_priv);
+}
+
+void intel_uncore_init_mmio(struct drm_i915_private *dev_priv)
+{
+ i915_check_vgpu(dev_priv);
+
+ intel_uncore_edram_detect(dev_priv);
+ intel_uncore_fw_domains_init_mmio(dev_priv);
+ __intel_uncore_early_sanitize(dev_priv, false);
+
+ dev_priv->uncore.unclaimed_mmio_check = 1;
+ dev_priv->uncore.pmic_bus_access_nb.notifier_call =
+ i915_pmic_bus_access_notifier;
+
iosf_mbi_register_pmic_bus_access_notifier(
&dev_priv->uncore.pmic_bus_access_nb);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 582771251b57..695ea5600469 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -128,7 +128,8 @@ struct intel_uncore {
void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
-void intel_uncore_init(struct drm_i915_private *dev_priv);
+void intel_uncore_init_early(struct drm_i915_private *dev_priv);
+void intel_uncore_init_mmio(struct drm_i915_private *dev_priv);
bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
void intel_uncore_fini(struct drm_i915_private *dev_priv);
--
2.15.0.rc0
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