[PATCH 09/13] drm/i915: Program gen3- watermarks atomically
Maarten Lankhorst
maarten.lankhorst at linux.intel.com
Thu Sep 7 09:29:45 UTC 2017
With the atomic watermark calculations calculate intermediary watermark
values and update the watermarks atomically.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_pm.c | 241 +++++++++++++++++++++++++++++----------
3 files changed, 191 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ff4bb67c3f70..0bc21a4ae137 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1802,6 +1802,10 @@ struct g4x_wm_values {
bool fbc_en;
};
+struct i9xx_wm_values {
+ bool cxsr;
+};
+
struct skl_ddb_entry {
uint16_t start, end; /* in number of blocks, 'end' is exclusive */
};
@@ -2469,6 +2473,7 @@ struct drm_i915_private {
struct skl_wm_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
+ struct i9xx_wm_values i9xx;
};
uint8_t max_level;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c78c712d5774..4114e09f6e93 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -555,7 +555,8 @@ struct i9xx_wm_state {
struct {
uint16_t plane_wm;
- } sr;
+ uint16_t cursor_wm;
+ } sr, hpll;
};
struct intel_crtc_wm_state {
@@ -604,7 +605,7 @@ struct intel_crtc_wm_state {
} g4x;
struct {
- struct i9xx_wm_state optimal;
+ struct i9xx_wm_state optimal, intermediate;
} i9xx;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index feb67889e5c6..631c890ae911 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -453,6 +453,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
dev_priv->wm.vlv.cxsr = enable;
else if (IS_G4X(dev_priv))
dev_priv->wm.g4x.cxsr = enable;
+ else if (INTEL_GEN(dev_priv) <= 4)
+ dev_priv->wm.i9xx.cxsr = enable;
mutex_unlock(&dev_priv->wm.wm_mutex);
return ret;
@@ -840,13 +842,17 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
return enabled;
}
-static void pineview_update_wm(struct intel_crtc *unused_crtc)
+static int pnv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
- struct intel_crtc *crtc;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct i9xx_wm_state *wm_state = &crtc_state->wm.i9xx.optimal;
+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
+ const struct drm_plane_state *primary_plane_state = NULL;
const struct cxsr_latency *latency;
- u32 reg;
- unsigned int wm;
+
+ memset(wm_state, 0, sizeof(*wm_state));
latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
dev_priv->is_ddr3,
@@ -854,60 +860,94 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
dev_priv->mem_freq);
if (!latency) {
DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
- intel_set_memory_cxsr(dev_priv, false);
- return;
+
+ return 0;
}
- crtc = single_enabled_crtc(dev_priv);
- if (crtc) {
- const struct drm_display_mode *adjusted_mode =
- &crtc->config->base.adjusted_mode;
+ if (crtc_state->base.plane_mask & BIT(drm_plane_index(&plane->base)))
+ primary_plane_state = __drm_atomic_get_current_plane_state(&state->base, &plane->base);
+
+ if (primary_plane_state) {
const struct drm_framebuffer *fb =
- crtc->base.primary->state->fb;
+ primary_plane_state->fb;
int cpp = fb->format->cpp[0];
- int clock = adjusted_mode->crtc_clock;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+ unsigned active_crtcs;
+
+ if (state->modeset)
+ active_crtcs = state->active_crtcs;
+ else
+ active_crtcs = dev_priv->active_crtcs;
+
+ wm_state->cxsr = active_crtcs == drm_crtc_mask(&crtc->base);
+
+ wm_state->sr.plane_wm =
+ intel_calculate_wm(adjusted_mode->crtc_clock,
+ &pineview_display_wm,
+ pineview_display_wm.fifo_size,
+ cpp, latency->display_sr);
+
+ wm_state->sr.cursor_wm =
+ intel_calculate_wm(adjusted_mode->crtc_clock,
+ &pineview_cursor_wm,
+ pineview_display_wm.fifo_size,
+ 4, latency->cursor_sr);
+
+ wm_state->hpll.plane_wm =
+ intel_calculate_wm(adjusted_mode->crtc_clock,
+ &pineview_display_hplloff_wm,
+ pineview_display_hplloff_wm.fifo_size,
+ cpp, latency->display_hpll_disable);
+
+ wm_state->hpll.cursor_wm =
+ intel_calculate_wm(adjusted_mode->crtc_clock,
+ &pineview_cursor_hplloff_wm,
+ pineview_display_hplloff_wm.fifo_size,
+ 4, latency->cursor_hpll_disable);
+
+ DRM_DEBUG_KMS("FIFO watermarks - can cxsr: %s, display plane %d, cursor SR size: %d\n",
+ yesno(wm_state->cxsr), wm_state->sr.plane_wm, wm_state->sr.cursor_wm);
+ } else
+ wm_state->cxsr = false;
+
+ return 0;
+}
+
+static void pnv_program_watermarks(struct drm_i915_private *dev_priv)
+{
+ struct intel_crtc *crtc;
+ struct i9xx_wm_state *wm_state = NULL;
+
+ crtc = single_enabled_crtc(dev_priv);
+ if (crtc)
+ wm_state = &crtc->wm.active.i9xx;
+
+ if (wm_state && wm_state->cxsr) {
+ u32 reg;
/* Display SR */
- wm = intel_calculate_wm(clock, &pineview_display_wm,
- pineview_display_wm.fifo_size,
- cpp, latency->display_sr);
reg = I915_READ(DSPFW1);
reg &= ~DSPFW_SR_MASK;
- reg |= FW_WM(wm, SR);
+ reg |= FW_WM(wm_state->sr.plane_wm, SR);
I915_WRITE(DSPFW1, reg);
DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
/* cursor SR */
- wm = intel_calculate_wm(clock, &pineview_cursor_wm,
- pineview_display_wm.fifo_size,
- 4, latency->cursor_sr);
reg = I915_READ(DSPFW3);
- reg &= ~DSPFW_CURSOR_SR_MASK;
- reg |= FW_WM(wm, CURSOR_SR);
+ reg &= ~(DSPFW_CURSOR_SR_MASK | DSPFW_HPLL_SR_MASK | DSPFW_HPLL_CURSOR_MASK);
+ reg |= FW_WM(wm_state->sr.cursor_wm, CURSOR_SR);
+ reg |= FW_WM(wm_state->hpll.plane_wm, HPLL_SR);
+ reg |= FW_WM(wm_state->hpll.cursor_wm, HPLL_SR);
I915_WRITE(DSPFW3, reg);
- /* Display HPLL off SR */
- wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
- pineview_display_hplloff_wm.fifo_size,
- cpp, latency->display_hpll_disable);
- reg = I915_READ(DSPFW3);
- reg &= ~DSPFW_HPLL_SR_MASK;
- reg |= FW_WM(wm, HPLL_SR);
- I915_WRITE(DSPFW3, reg);
-
- /* cursor HPLL off SR */
- wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
- pineview_display_hplloff_wm.fifo_size,
- 4, latency->cursor_hpll_disable);
- reg = I915_READ(DSPFW3);
- reg &= ~DSPFW_HPLL_CURSOR_MASK;
- reg |= FW_WM(wm, HPLL_CURSOR);
- I915_WRITE(DSPFW3, reg);
DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
- intel_set_memory_cxsr(dev_priv, true);
+ _intel_set_memory_cxsr(dev_priv, true);
+ dev_priv->wm.i9xx.cxsr = true;
} else {
- intel_set_memory_cxsr(dev_priv, false);
+ _intel_set_memory_cxsr(dev_priv, false);
+ dev_priv->wm.i9xx.cxsr = false;
}
}
@@ -2329,6 +2369,47 @@ static int i9xx_compute_pipe_wm(struct intel_crtc_state *crtc_state)
return 0;
}
+static int i9xx_compute_intermediate_wm(struct drm_device *dev,
+ struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *newstate)
+{
+ struct i9xx_wm_state *intermediate = &newstate->wm.i9xx.intermediate;
+ const struct drm_crtc_state *old_drm_state =
+ drm_atomic_get_old_crtc_state(newstate->base.state, &intel_crtc->base);
+ const struct i9xx_wm_state *old = &to_intel_crtc_state(old_drm_state)->wm.i9xx.optimal;
+ const struct i9xx_wm_state *optimal = &newstate->wm.i9xx.optimal;
+
+ /*
+ * Start with the final, target watermarks, then combine with the
+ * currently active watermarks to get values that are safe both before
+ * and after the vblank.
+ */
+ *intermediate = *optimal;
+ if (newstate->disable_cxsr)
+ intermediate->cxsr = false;
+
+ if (!newstate->base.active ||
+ drm_atomic_crtc_needs_modeset(&newstate->base))
+ goto out;
+
+ intermediate->plane_wm = min(old->plane_wm, optimal->plane_wm);
+ intermediate->sr.plane_wm = min(old->sr.plane_wm, optimal->sr.plane_wm);
+ intermediate->sr.cursor_wm = min(old->sr.cursor_wm, optimal->sr.cursor_wm);
+ intermediate->hpll.plane_wm = min(old->hpll.plane_wm, optimal->hpll.plane_wm);
+ intermediate->hpll.cursor_wm = min(old->hpll.cursor_wm, optimal->hpll.cursor_wm);
+
+out:
+ /*
+ * If our intermediate WM are identical to the final WM, then we can
+ * omit the post-vblank programming; only update if it's different.
+ */
+ if (newstate->base.active &&
+ memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
+ newstate->wm.need_postvbl_update = true;
+
+ return 0;
+}
+
void i9xx_wm_get_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -2357,17 +2438,15 @@ void i9xx_wm_get_hw_state(struct drm_device *dev)
}
}
-static void i9xx_update_wm(struct intel_crtc *crtc)
+static void i9xx_program_watermarks(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc *crtc;
uint32_t fwater_lo;
uint32_t fwater_hi;
int cwm, srwm = -1;
int planea_wm, planeb_wm;
struct intel_crtc *enabled = NULL;
- crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
-
crtc = intel_get_crtc_for_plane(dev_priv, 0);
planea_wm = crtc->wm.active.i9xx.plane_wm;
if (intel_crtc_active(crtc))
@@ -2393,7 +2472,7 @@ static void i9xx_update_wm(struct intel_crtc *crtc)
cwm = 2;
/* Play safe and disable self-refresh before adjusting watermarks. */
- intel_set_memory_cxsr(dev_priv, false);
+ _intel_set_memory_cxsr(dev_priv, false);
/* Calc sr entries for one plane configs */
if (enabled && enabled->wm.active.i9xx.cxsr) {
@@ -2420,19 +2499,17 @@ static void i9xx_update_wm(struct intel_crtc *crtc)
I915_WRITE(FW_BLC2, fwater_hi);
if (enabled)
- intel_set_memory_cxsr(dev_priv, true);
+ _intel_set_memory_cxsr(dev_priv, true);
+
+ dev_priv->wm.i9xx.cxsr = enabled;
}
-static void i845_update_wm(struct intel_crtc *crtc)
+static void i845_program_watermarks(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
uint32_t fwater_lo;
int planea_wm;
- if (!intel_crtc_active(crtc))
- return;
-
- crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
planea_wm = crtc->wm.active.i9xx.plane_wm;
fwater_lo = I915_READ(FW_BLC) & ~0xfff;
@@ -2443,6 +2520,45 @@ static void i845_update_wm(struct intel_crtc *crtc)
I915_WRITE(FW_BLC, fwater_lo);
}
+
+static void i9xx_initial_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+
+ mutex_lock(&dev_priv->wm.wm_mutex);
+ crtc->wm.active.i9xx = crtc_state->wm.i9xx.intermediate;
+ if (IS_PINEVIEW(dev_priv))
+ pnv_program_watermarks(dev_priv);
+ else if (INTEL_INFO(dev_priv)->num_pipes == 1)
+ i845_program_watermarks(intel_crtc);
+ else
+ i9xx_program_watermarks(dev_priv);
+ mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
+static void i9xx_optimize_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+
+ if (!crtc_state->wm.need_postvbl_update)
+ return;
+
+ mutex_lock(&dev_priv->wm.wm_mutex);
+ intel_crtc->wm.active.i9xx = crtc_state->wm.i9xx.optimal;
+ if (IS_PINEVIEW(dev_priv))
+ pnv_program_watermarks(dev_priv);
+ else if (INTEL_INFO(dev_priv)->num_pipes == 1)
+ i845_program_watermarks(intel_crtc);
+ else
+ i9xx_program_watermarks(dev_priv);
+ mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
/* latency must be in 0.1us units. */
static unsigned int ilk_wm_method1(unsigned int pixel_rate,
unsigned int cpp,
@@ -8904,24 +9020,33 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->fsb_freq, dev_priv->mem_freq);
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
- dev_priv->display.update_wm = NULL;
- } else
- dev_priv->display.update_wm = pineview_update_wm;
+ dev_priv->display.compute_pipe_wm = NULL;
+ dev_priv->display.initial_watermarks = NULL;
+ dev_priv->display.optimize_watermarks = NULL;
+ } else {
+ dev_priv->display.compute_pipe_wm = pnv_compute_pipe_wm;
+ dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+ dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
+ }
} else if (IS_GEN4(dev_priv)) {
dev_priv->display.update_wm = i965_update_wm;
} else if (IS_GEN3(dev_priv)) {
dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
- dev_priv->display.update_wm = i9xx_update_wm;
+ dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
+
+ dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+ dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (IS_GEN2(dev_priv)) {
dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
+ dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
+ dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+ dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
if (INTEL_INFO(dev_priv)->num_pipes == 1) {
- dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size;
} else {
- dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i830_get_fifo_size;
}
} else {
--
2.11.0
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