[PATCH 7/7] drm/i915/skl+: make sure higher latency level has higher WM value

Mahesh Kumar mahesh1.kumar at intel.com
Fri Sep 8 10:33:52 UTC 2017


Signed-off-by: Mahesh Kumar <mahesh1.kumar at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 46a17f9825f6..82ec01b7863e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4562,6 +4562,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		} else {
 			res_blocks++;
 		}
+
+		/*
+		 * Make sure result blocks for higher latency levels are atleast
+		 * as high as level below.
+		 * Assumption in new DDB algorithm.
+		 * Also covers Display WA #1125 for RC.
+		 */
+		if (result[level - 1]->plane_res_b > res_blocks)
+			res_blocks = result[level - 1]->plane_res_b;
 	}
 
 	if (res_blocks >= ddb_allocation || res_lines > 31) {
-- 
2.13.0



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