[PATCH 36/38] bsw-irq2

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_irq.c | 59 ++++++++++++++++-------------------------
 1 file changed, 23 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d58fa40e922e..67e7d78eb659 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1331,37 +1331,22 @@ static void gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
 {
 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
 		gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
-		if (likely(gt_iir[0]))
-			I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
-		else
-			DRM_ERROR("The master control interrupt lied (GT0)!\n");
+		I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
 	}
 
 	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
 		gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
-		if (likely(gt_iir[1]))
-			I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
-		else
-			DRM_ERROR("The master control interrupt lied (GT1)!\n");
+		I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
 	}
 
 	if (master_ctl & GEN8_GT_VECS_IRQ) {
 		gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
-		if (likely(gt_iir[3]))
-			I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
-		else
-			DRM_ERROR("The master control interrupt lied (GT3)!\n");
+		I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
 	}
 
 	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
 		gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
-		if (likely(gt_iir[2] & (dev_priv->pm_rps_events |
-					dev_priv->pm_guc_events)))
-			I915_WRITE_FW(GEN8_GT_IIR(2),
-				      gt_iir[2] & (dev_priv->pm_rps_events |
-						   dev_priv->pm_guc_events));
-		else
-			DRM_ERROR("The master control interrupt lied (PM)!\n");
+		I915_WRITE_FW(GEN8_GT_IIR(2), gt_iir[2]);
 	}
 }
 
@@ -1745,8 +1730,10 @@ static bool valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 		if (iir & iir_bit)
 			mask |= dev_priv->pipestat_irq_mask[pipe];
 
-		if (!mask)
+		if (!mask) {
+			pipe_stats[pipe] = 0;
 			continue;
+		}
 
 		reg = PIPESTAT(pipe);
 		mask |= PIPESTAT_INT_ENABLE_MASK;
@@ -1841,7 +1828,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 
 	do {
 		u32 iir, gt_iir, pm_iir;
-		u32 pipe_stats[I915_MAX_PIPES] = {};
+		u32 pipe_stats[I915_MAX_PIPES];
 		u32 hotplug_status = 0;
 		u32 ier = 0;
 
@@ -1928,20 +1915,11 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
 	do {
 		u32 master_ctl, iir;
-		u32 gt_iir[4] = {};
-		u32 pipe_stats[I915_MAX_PIPES] = {};
+		u32 gt_iir[4];
+		u32 pipe_stats[I915_MAX_PIPES];
 		u32 hotplug_status = 0;
-		u32 ier = 0;
 		bool has_pipe_stats = false;
 
-		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
-		iir = I915_READ(VLV_IIR);
-
-		if (master_ctl == 0 && iir == 0)
-			break;
-
-		ret = IRQ_HANDLED;
-
 		/*
 		 * Theory on interrupt generation, based on empirical evidence:
 		 *
@@ -1955,9 +1933,20 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
 		 * bits this time around.
 		 */
-		I915_WRITE(GEN8_MASTER_IRQ, 0);
+		master_ctl = I915_READ(GEN8_MASTER_IRQ);
+		if (master_ctl & ~GEN8_MASTER_IRQ_CONTROL) {
+			I915_WRITE(GEN8_MASTER_IRQ, 0);
+
+			gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
+
+			I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+			ret = IRQ_HANDLED;
+		}
 
+		iir = I915_READ(VLV_IIR);
 		if (iir) {
+			u32 ier;
+
 			ier = I915_READ(VLV_IER);
 			I915_WRITE(VLV_IER, 0);
 
@@ -1980,11 +1969,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 			 */
 			I915_WRITE(VLV_IIR, iir);
 			I915_WRITE(VLV_IER, ier);
+			ret = IRQ_HANDLED;
 		}
 
-		gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
-		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
-
 		gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
 
 		if (hotplug_status)
-- 
2.14.1