[PATCH 37/38] bsw-irq3

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_irq.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 67e7d78eb659..4e58737827f0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1906,6 +1906,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 	struct drm_device *dev = arg;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	irqreturn_t ret = IRQ_NONE;
+	u32 master_ctl;
 
 	if (!intel_irqs_enabled(dev_priv))
 		return IRQ_NONE;
@@ -1913,9 +1914,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	disable_rpm_wakeref_asserts(dev_priv);
 
+	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
 	do {
-		u32 master_ctl, iir;
-		u32 gt_iir[4];
+		u32 gt_iir[4], iir;
 		u32 pipe_stats[I915_MAX_PIPES];
 		u32 hotplug_status = 0;
 		bool has_pipe_stats = false;
@@ -1933,22 +1934,21 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
 		 * bits this time around.
 		 */
-		master_ctl = I915_READ(GEN8_MASTER_IRQ);
 		if (master_ctl & ~GEN8_MASTER_IRQ_CONTROL) {
-			I915_WRITE(GEN8_MASTER_IRQ, 0);
+			I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
 
 			gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
 
-			I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+			I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 			ret = IRQ_HANDLED;
 		}
 
-		iir = I915_READ(VLV_IIR);
+		iir = I915_READ_FW(VLV_IIR);
 		if (iir) {
 			u32 ier;
 
-			ier = I915_READ(VLV_IER);
-			I915_WRITE(VLV_IER, 0);
+			ier = I915_READ_FW(VLV_IER);
+			I915_WRITE_FW(VLV_IER, 0);
 
 			if (iir & I915_DISPLAY_PORT_INTERRUPT)
 				hotplug_status = i9xx_hpd_irq_ack(dev_priv);
@@ -1967,8 +1967,8 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 			 * VLV_IIR is single buffered, and reflects the level
 			 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
 			 */
-			I915_WRITE(VLV_IIR, iir);
-			I915_WRITE(VLV_IER, ier);
+			I915_WRITE_FW(VLV_IIR, iir);
+			I915_WRITE_FW(VLV_IER, ier);
 			ret = IRQ_HANDLED;
 		}
 
@@ -1979,7 +1979,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
 		if (has_pipe_stats)
 			valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
-	} while (0);
+
+		master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
+	} while (master_ctl & ~GEN8_MASTER_IRQ_CONTROL);
 
 	enable_rpm_wakeref_asserts(dev_priv);
 
-- 
2.14.1