✗ Fi.CI.BAT: failure for series starting with [01/53] drm/i915/execlists: Set queue priority from secondary port
Patchwork
patchwork at emeril.freedesktop.org
Wed Apr 11 15:43:48 UTC 2018
== Series Details ==
Series: series starting with [01/53] drm/i915/execlists: Set queue priority from secondary port
URL : https://patchwork.freedesktop.org/series/41552/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4046 -> Trybot_2023 =
== Summary - FAILURE ==
Serious unknown changes coming with Trybot_2023 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Trybot_2023, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2023/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Trybot_2023:
=== IGT changes ===
==== Possible regressions ====
igt at gem_exec_suspend@basic-s3:
fi-skl-guc: PASS -> FAIL
igt at gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: PASS -> INCOMPLETE
==== Warnings ====
igt at gem_ctx_create@basic:
fi-elk-e7500: SKIP -> PASS +6
igt at gem_ctx_exec@basic:
fi-ilk-650: SKIP -> PASS +6
fi-bwr-2160: SKIP -> PASS +6
== Known issues ==
Here are the changes found in Trybot_2023 that come from known issues:
=== IGT changes ===
==== Possible fixes ====
igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-cfl-s3: INCOMPLETE (fdo#105641) -> PASS
fdo#105641 https://bugs.freedesktop.org/show_bug.cgi?id=105641
== Participating hosts (34 -> 32) ==
Missing (2): fi-ilk-m540 fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4046 -> Trybot_2023
CI_DRM_4046: d123888920ccd112851ade43a3bf1c25627c2316 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4422: a914075d55dd089095121906bf4c3e825a3cecf2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Trybot_2023: 5f1ef116dbe23ab994cc9cd9e7f2472c7ab82709 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4422: 45e115f293fd6acc0c9647cf2d3b76be78819ba5 @ git://anongit.freedesktop.org/piglit
== Linux commits ==
5f1ef116dbe2 drm/i915: Support per-context user requests for GPU frequency control
823c27367e8c drm/i915: Remove unwarranted clamping for hsw/bdw
229c762db23a drm/i915,intel_ips: Enable GPU wait-boosting with IPS
150781d97cb4 drm/i915: Pull IPS into GT power management
08c7fe20b01b drm/i915: Rename rps min/max frequencies
c8fc10c8927d drm/i915: Refactor frequency bounds computation
ea784da44412 drm/i915: Simplify rc6/rps enabling
05d5c83a00c2 drm/i915: Enabling rc6 and rps have different requirements, so separate them
e0df5cf5dbdd drm/i915: Split control of rps and rc6
2ee4e43a5037 drm/i915: Reorder GT interface code
5062662fce73 drm/i915: Remove defunct intel_suspend_gt_powersave()
0498313fe363 drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
4a4c0ab690e3 drm/i915: Move all the RPS irq handlers to intel_gt_pm
aeeed6a14163 drm/i915: Move rps worker to intel_gt_pm.c
406c14dea3d4 drm/i915: Split GT powermanagement functions to intel_gt_pm.c
2e1fdd5ffb3b drm/i915: Remove obsolete min/max freq setters from debugfs
f67bbc339716 drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
8b93dd4ec324 drm/i915: Enable render context support for Ironlake (gen5)
225d83426c3f drm/i915: Generalize i915_gem_sanitize() to reset contexts
c4afcba65780 drm/i915: Record logical context support in driver caps
4bd7e54adc5c drm/i915: Mark up Ironlake ips with rpm wakerefs
734dd39b1bd7 drm/i915: Move sandybride pcode access to intel_sideband.c
fbc3b68057e7 drm/i915: Merge sandybridge_pcode_(read|write)
caf6f7ed5690 drm/i915: Merge sbi read/write into a single accessor
e157d2a5158a drm/i915: Separate sideband declarations to intel_sideband.h
5b7b297bcf16 drm/i915: Replace pcu_lock with sb_lock
be7d47a89e65 Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
28a838513f21 drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
be0445e1bcd9 drm/i915: Lift sideband locking for vlv_punit_(read|write)
92687eff6ebb drm/i915: Lift acquiring the vlv punit magic to a common sb-get
840a5121690d drm/i915: Disable preemption and sleeping while using the punit sideband
b79cbb4adc21 drm/i915: Request driver probe from an async task
683f79c5861a drm/i915/execlists: Delay updating ring register state after resume
2e147b5b0a58 sigh
c98833202139 drm/i915: Allow user control over preempt timeout on their important context
af08b0d31295 drm/i915: Use a preemption timeout to enforce interactivity
acfb34a8521a drm/i915/preemption: Select timeout when scheduling
88dd03e41e4b drm/i915/execlists: Try preempt-reset from hardirq timer context
6c7ebefdaab8 drm/i915/execlists: Force preemption via reset on timeout
a7a00e0fe024 drm/i915: Compile out engine debug for release
f0987bb13dbf drm/i915: Allow init_breadcrumbs to be used from irq context
360476b8bfe0 drm/i915/guc: Make submission tasklet hardirq safe
7db76f44d8bd drm/i915/execlists: Make submission tasklet hardirq safe
31daa7790045 drm/i915: Be irqsafe inside reset
fd567ff40016 drm/i915: Stop parking the signaler around reset
ec7b49774c5a drm/i915: Combine tasklet_kill and tasklet_disable
5fd2bbdbdc4d drm/i915/breadcrumbs: Keep the fake irq armed across reset
127e370b9250 drm/i915/execlists: Flush pending preemption events during reset
b7e473bf7bdf drm/i915: Split execlists/guc reset preparations
e78771ed31f7 drm/i915: Move engine reset prepare/finish to backends
1eda154a4d9d drm/i915/execlists: Refactor out complete_preempt_context()
e9f7d85b77b4 drm/i915/selftests: Wait for idle between idle resets as well
09487e6dce40 drm/i915/execlists: Set queue priority from secondary port
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2023/issues.html
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