[PATCH v1 6/6] drm/i915: Enable Display WA 0528
Srinivas, Vidya
vidya.srinivas at intel.com
Thu Apr 12 09:42:26 UTC 2018
> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst at linux.intel.com]
> Sent: Thursday, April 12, 2018 3:07 PM
> To: Srinivas, Vidya <vidya.srinivas at intel.com>; intel-gfx-
> trybot at lists.freedesktop.org
> Cc: Kamath, Sunil <sunil.kamath at intel.com>; Saarinen, Jani
> <jani.saarinen at intel.com>
> Subject: Re: [PATCH v1 6/6] drm/i915: Enable Display WA 0528
>
> Op 12-04-18 om 10:59 schreef Vidya Srinivas:
> > Possible hang with NV12 plane surface formats.
> > WA: When the plane source pixel format is NV12, the CHICKEN_PIPESL_*
> > register bit 22 must be set to 1 and the render decompression must not
> > be enabled on any of the planes in that pipe.
> >
> > v2: removed unnecessary POSTING_READ
> >
> > Credits-to: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++--
> > 1 file changed, 18 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 42ce330..6d159ac 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -505,6 +505,18 @@ static const struct intel_limit intel_limits_bxt
> > = { };
> >
> > static void
> > +skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
> > +{
> > + if (IS_SKYLAKE(dev_priv))
> > + return;
> > +
> > + if (enable)
> > + I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
> > + else
> > + I915_WRITE(CHICKEN_PIPESL_1(pipe), ~HSW_FBCQ_DIS);
> Shouldn't yo uwrite 0 here?
Sure, thank you. I was just thinking it shouldn’t clear other bits if they were
Enabled earlier. But we are not using other bits I think. I will update the patch
As suggested.
Regards
Vidya
>
> ~Maarten
> > +}
> > +
> > +static void
> > skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool
> > enable) {
> > if (IS_SKYLAKE(dev_priv))
> > @@ -5202,8 +5214,10 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >
> > /* Display WA 827 */
> > if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> > - !needs_nv12_wa(dev_priv, pipe_config))
> > + !needs_nv12_wa(dev_priv, pipe_config)) {
> > skl_wa_clkgate(dev_priv, crtc->pipe, false);
> > + skl_wa_528(dev_priv, crtc->pipe, false);
> > + }
> > }
> >
> > static void intel_pre_plane_update(struct intel_crtc_state
> > *old_crtc_state, @@ -5240,8 +5254,10 @@ static void
> > intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> >
> > /* Display WA 827 */
> > if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
> > - needs_nv12_wa(dev_priv, pipe_config))
> > + needs_nv12_wa(dev_priv, pipe_config)) {
> > skl_wa_clkgate(dev_priv, crtc->pipe, true);
> > + skl_wa_528(dev_priv, crtc->pipe, true);
> > + }
> >
> > /*
> > * Vblank time updates from the shadow to live plane control
> > register
>
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