[PATCH 2/2] whitelist-once

[Chris Wilson]

---
 drivers/gpu/drm/i915/intel_lrc.c         |  4 --
 drivers/gpu/drm/i915/intel_ringbuffer.c  |  2 -
 drivers/gpu/drm/i915/intel_workarounds.c | 68 +++++++++++-------------
 drivers/gpu/drm/i915/intel_workarounds.h |  2 -
 4 files changed, 32 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4f728587a756..e8e9b730aad6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1744,8 +1744,6 @@ static int gen8_init_render_ring(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
-	intel_whitelist_workarounds_apply(engine);
-
 	/* We need to disable the AsyncFlip performance optimisations in order
 	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 	 * programmed to '1' on all products.
@@ -1767,8 +1765,6 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
-	intel_whitelist_workarounds_apply(engine);
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c68ac605b8a9..d2ac4435c199 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -618,8 +618,6 @@ static int init_render_ring(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
-	intel_whitelist_workarounds_apply(engine);
-
 	/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 	if (IS_GEN(dev_priv, 4, 6))
 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ea0c68f77ea9..69125cb4c6d9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -475,37 +475,31 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static int intel_whitelist_workarounds_emit(struct i915_request *rq);
+
 int intel_ctx_workarounds_emit(struct i915_request *rq)
 {
 	struct i915_workarounds *w = &rq->i915->workarounds;
-	u32 *cs;
-	int ret, i;
 
-	if (w->count == 0)
-		return 0;
+	if (w->count) {
+		u32 *cs;
+		int i;
 
-	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
-	if (ret)
-		return ret;
+		cs = intel_ring_begin(rq, (w->count * 2 + 2));
+		if (IS_ERR(cs))
+			return PTR_ERR(cs);
 
-	cs = intel_ring_begin(rq, (w->count * 2 + 2));
-	if (IS_ERR(cs))
-		return PTR_ERR(cs);
+		*cs++ = MI_LOAD_REGISTER_IMM(w->count);
+		for (i = 0; i < w->count; i++) {
+			*cs++ = i915_mmio_reg_offset(w->reg[i].addr);
+			*cs++ = w->reg[i].value;
+		}
+		*cs++ = MI_NOOP;
 
-	*cs++ = MI_LOAD_REGISTER_IMM(w->count);
-	for (i = 0; i < w->count; i++) {
-		*cs++ = i915_mmio_reg_offset(w->reg[i].addr);
-		*cs++ = w->reg[i].value;
+		intel_ring_advance(rq, cs);
 	}
-	*cs++ = MI_NOOP;
 
-	intel_ring_advance(rq, cs);
-
-	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
-	if (ret)
-		return ret;
-
-	return 0;
+	return intel_whitelist_workarounds_emit(rq);
 }
 
 static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
@@ -802,31 +796,33 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
 	return wa;
 }
 
-static void whitelist_apply(struct intel_engine_cs *engine,
-			    const struct whitelist *wa)
+static int whitelist_emit(struct i915_request *rq, const struct whitelist *wa)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
-	const u32 base = engine->mmio_base;
+	const u32 base = rq->engine->mmio_base;
 	unsigned int i;
+	u32 *cs;
 
-	intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
+	cs = intel_ring_begin(rq, wa->count * 2 + 2);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
 
-	for (i = 0; i < wa->count; i++)
-		I915_WRITE_FW(RING_FORCE_TO_NONPRIV(base, i),
-			      i915_mmio_reg_offset(wa->reg[i]));
+	*cs++ = MI_LOAD_REGISTER_IMM(wa->count);
+	for (i = 0; i < wa->count; i++) {
+		*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
+		*cs++ = i915_mmio_reg_offset(wa->reg[i]);
+	}
+	*cs++ = MI_NOOP;
 
-	/* And clear the rest just in case of garbage */
-	for (; i < RING_MAX_NONPRIV_SLOTS; i++)
-		I915_WRITE_FW(RING_FORCE_TO_NONPRIV(base, i), 0);
+	intel_ring_advance(rq, cs);
 
-	intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
+	return 0;
 }
 
-void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
+static int intel_whitelist_workarounds_emit(struct i915_request *rq)
 {
 	struct whitelist wa;
 
-	whitelist_apply(engine, whitelist_build(engine, &wa));
+	return whitelist_emit(rq, whitelist_build(rq->engine, &wa));
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.h b/drivers/gpu/drm/i915/intel_workarounds.h
index b11d0623e626..90503ad0c226 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/intel_workarounds.h
@@ -12,6 +12,4 @@ int intel_ctx_workarounds_emit(struct i915_request *rq);
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
 
-void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
-
 #endif
-- 
2.17.0