✗ Fi.CI.BAT: failure for series starting with [01/54] drm/i915: Check whitelist registers across resets

Patchwork patchwork at emeril.freedesktop.org
Thu Apr 12 18:10:51 UTC 2018 

== Series Details ==

Series: series starting with [01/54] drm/i915: Check whitelist registers across resets
URL   : https://patchwork.freedesktop.org/series/41637/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4049 -> Trybot_2035 =

== Summary - FAILURE ==

  Serious unknown changes coming with Trybot_2035 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Trybot_2035, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41637/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Trybot_2035:

  === IGT changes ===

    ==== Possible regressions ====

    igt at drv_module_reload@basic-reload-inject:
      fi-bxt-j4205:       PASS -> DMESG-FAIL

    igt at gem_exec_suspend@basic-s3:
      fi-skl-guc:         PASS -> FAIL

    
    ==== Warnings ====

    igt at gem_ctx_create@basic:
      fi-elk-e7500:       SKIP -> PASS +6

    igt at gem_ctx_exec@basic:
      fi-ilk-650:         SKIP -> PASS +6
      fi-bwr-2160:        SKIP -> PASS +6

    igt at gem_exec_gttfill@basic:
      fi-pnv-d510:        PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Trybot_2035 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt at debugfs_test@read_all_entries:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    igt at gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    igt at prime_vgem@basic-fence-flip:
      fi-ilk-650:         PASS -> FAIL (fdo#104008)

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008


== Participating hosts (35 -> 33) ==

  Additional (1): fi-cnl-y3 
  Missing    (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4049 -> Trybot_2035

  CI_DRM_4049: 3dbfa04d62f1f1214a03c3b2d30f987dccf50ab4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4426: d502f055ac4500cada758876a512ac4f14b34851 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Trybot_2035: 5596716eda3fb844e26c6ad277f21e8dd829e12c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4426: 93b35926a150e318439d2505901288594b3548f5 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

5596716eda3f drm/i915: Support per-context user requests for GPU frequency control
c776baa40246 drm/i915: Remove unwarranted clamping for hsw/bdw
7eab2b417af4 drm/i915,intel_ips: Enable GPU wait-boosting with IPS
dc5d87a6d3bd drm/i915: Pull IPS into GT power management
8de60bf4d815 drm/i915: Rename rps min/max frequencies
cf38c34a08a4 drm/i915: Refactor frequency bounds computation
0ae5e6958382 drm/i915: Simplify rc6/rps enabling
6eefdcdd1b8d drm/i915: Enabling rc6 and rps have different requirements, so separate them
c11a50bc22d3 drm/i915: Split control of rps and rc6
eb0e5dfb5411 drm/i915: Reorder GT interface code
6e36ef0b1474 drm/i915: Remove defunct intel_suspend_gt_powersave()
c01e6e8d8efc drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
425c4eedc00b drm/i915: Move all the RPS irq handlers to intel_gt_pm
31acc36b97d6 drm/i915: Move rps worker to intel_gt_pm.c
0de21b869288 drm/i915: Split GT powermanagement functions to intel_gt_pm.c
e6c96b2cfcbf drm/i915: Remove obsolete min/max freq setters from debugfs
795609af8b0f drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
c8bb8bc16ba0 drm/i915: Enable render context support for Ironlake (gen5)
0019b1d2c660 drm/i915: Generalize i915_gem_sanitize() to reset contexts
3031e7bc0a73 drm/i915: Record logical context support in driver caps
7fd30dbff843 drm/i915: Mark up Ironlake ips with rpm wakerefs
5a48d7327a8a drm/i915: Move sandybride pcode access to intel_sideband.c
82881740cb7d drm/i915: Merge sandybridge_pcode_(read|write)
ae21d2c935f0 drm/i915: Merge sbi read/write into a single accessor
957f1417fb7a drm/i915: Separate sideband declarations to intel_sideband.h
9e9a721385fc drm/i915: Replace pcu_lock with sb_lock
866a8ee91fa2 Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
4c982925806d drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
bd6a86028e30 drm/i915: Lift sideband locking for vlv_punit_(read|write)
00ffa4c07b3c drm/i915: Lift acquiring the vlv punit magic to a common sb-get
579c23a8848e drm/i915: Disable preemption and sleeping while using the punit sideband
73ab3ca149f2 drm/i915: Request driver probe from an async task
b8ee14db4139 drm/i915/execlists: Delay updating ring register state after resume
be54eb9aad1d sigh
7a100b5403d5 drm/i915: Allow user control over preempt timeout on their important context
2bbe2e17bbc2 drm/i915: Use a preemption timeout to enforce interactivity
0d4e6d6959cc drm/i915/preemption: Select timeout when scheduling
4be6f9edc8cb drm/i915/execlists: Try preempt-reset from hardirq timer context
8468470e9aa5 drm/i915/execlists: Force preemption via reset on timeout
5ecbe829b9d1 drm/i915: Compile out engine debug for release
c6414b73fe44 drm/i915: Allow init_breadcrumbs to be used from irq context
03ea6283f51a drm/i915/guc: Make submission tasklet hardirq safe
e8e218ccdf62 drm/i915/execlists: Make submission tasklet hardirq safe
6166fbe9923e drm/i915: Be irqsafe inside reset
54e8bbfa83d9 drm/i915: Stop parking the signaler around reset
44375c6f5574 drm/i915: Combine tasklet_kill and tasklet_disable
b38a0d0ac33b drm/i915/breadcrumbs: Keep the fake irq armed across reset
aeca423ba86d drm/i915/execlists: Flush pending preemption events during reset
f457e92e1154 drm/i915: Split execlists/guc reset preparations
129e96bf26d3 drm/i915: Move engine reset prepare/finish to backends
1ee4235b2230 drm/i915/execlists: Refactor out complete_preempt_context()
175d03d2fc86 drm/i915/selftests: Wait for idle between idle resets as well
c204213a95a3 drm/i915: Pack params to engine->schedule() into a struct
0b28485da79d drm/i915: Check whitelist registers across resets

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2035/issues.html

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