✗ Fi.CI.BAT: failure for series starting with [01/54] drm/i915: Check whitelist registers across resets

Patchwork patchwork at emeril.freedesktop.org
Fri Apr 13 14:39:48 UTC 2018 

== Series Details ==

Series: series starting with [01/54] drm/i915: Check whitelist registers across resets
URL   : https://patchwork.freedesktop.org/series/41678/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4053 -> Trybot_2042 =

== Summary - FAILURE ==

  Serious unknown changes coming with Trybot_2042 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Trybot_2042, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/41678/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Trybot_2042:

  === IGT changes ===

    ==== Possible regressions ====

    igt at drv_module_reload@basic-reload:
      fi-bsw-n3050:       PASS -> DMESG-FAIL

    
    ==== Warnings ====

    igt at gem_ctx_create@basic:
      fi-elk-e7500:       SKIP -> PASS +6

    igt at gem_ctx_exec@basic:
      fi-ilk-650:         SKIP -> PASS +6
      fi-bwr-2160:        SKIP -> PASS +6

    
== Known issues ==

  Here are the changes found in Trybot_2042 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt at gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    igt at kms_chamelium@hdmi-hpd-fast:
      fi-kbl-7500u:       SKIP -> FAIL (fdo#102672, fdo#103841)

    igt at kms_frontbuffer_tracking@basic:
      fi-cnl-y3:          PASS -> FAIL (fdo#103167)

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841


== Participating hosts (35 -> 33) ==

  Missing    (2): fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4053 -> Trybot_2042

  CI_DRM_4053: e2599f775a9c1c27f702e90e6432e555764edcd8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4429: 80e4910581c7310258375a003a5de9a57ed24546 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Trybot_2042: 56d7562635238df95f51d53025e6d21f42442eef @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4429: 93b35926a150e318439d2505901288594b3548f5 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

56d756263523 drm/i915: Support per-context user requests for GPU frequency control
a8b5e442b6c2 drm/i915: Remove unwarranted clamping for hsw/bdw
34fb6fffc834 drm/i915,intel_ips: Enable GPU wait-boosting with IPS
4192b92fb660 drm/i915: Pull IPS into GT power management
9711e96eaef0 drm/i915: Rename rps min/max frequencies
c27a4a3a8d22 drm/i915: Refactor frequency bounds computation
06b7fd58e062 drm/i915: Simplify rc6/rps enabling
065b4baa1fe4 drm/i915: Enabling rc6 and rps have different requirements, so separate them
cf6353c28e13 drm/i915: Split control of rps and rc6
9ebb335499d5 drm/i915: Reorder GT interface code
52af49240b5f drm/i915: Remove defunct intel_suspend_gt_powersave()
ec658bf32a84 drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
09d8503c8df7 drm/i915: Move all the RPS irq handlers to intel_gt_pm
49ab25ab7a3c drm/i915: Move rps worker to intel_gt_pm.c
422e30ce204d drm/i915: Split GT powermanagement functions to intel_gt_pm.c
2cdefd4b5e69 drm/i915: Remove obsolete min/max freq setters from debugfs
3018f8d32315 drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
c9dcc066b208 drm/i915: Enable render context support for Ironlake (gen5)
dbfe85527fb9 drm/i915: Generalize i915_gem_sanitize() to reset contexts
0df240970ab2 drm/i915: Record logical context support in driver caps
fe5d21197759 drm/i915: Mark up Ironlake ips with rpm wakerefs
091dfa82f86f drm/i915: Move sandybride pcode access to intel_sideband.c
689256de2eb1 drm/i915: Merge sandybridge_pcode_(read|write)
7c4c0f594ca2 drm/i915: Merge sbi read/write into a single accessor
ea6f0b0bb62d drm/i915: Separate sideband declarations to intel_sideband.h
ad845d36902d drm/i915: Replace pcu_lock with sb_lock
3d381ec2cee4 Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
e706f91b7d5b drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
0b936abd8750 drm/i915: Lift sideband locking for vlv_punit_(read|write)
211822045e1f drm/i915: Lift acquiring the vlv punit magic to a common sb-get
698280a94e02 drm/i915: Disable preemption and sleeping while using the punit sideband
1877de31ee64 drm/i915: Request driver probe from an async task
eb60a4fee08e drm/i915/execlists: Delay updating ring register state after resume
e02c3b8bc30d sigh
565ef5f5c809 drm/i915: Allow user control over preempt timeout on their important context
df3ab8fbbee6 drm/i915: Use a preemption timeout to enforce interactivity
0d978cf3e7c4 drm/i915/preemption: Select timeout when scheduling
ffd654bb0d57 drm/i915/execlists: Try preempt-reset from hardirq timer context
1fdaecf39baa drm/i915/execlists: Force preemption via reset on timeout
add4163eb98f drm/i915: Compile out engine debug for release
792b520c0c10 drm/i915: Allow init_breadcrumbs to be used from irq context
32a51b9d2732 drm/i915/guc: Make submission tasklet hardirq safe
09812165cd99 drm/i915/execlists: Make submission tasklet hardirq safe
a38d28203115 drm/i915: Be irqsafe inside reset
54e63625c806 drm/i915: Stop parking the signaler around reset
510962c25139 drm/i915: Combine tasklet_kill and tasklet_disable
e144d9512d75 drm/i915/breadcrumbs: Keep the fake irq armed across reset
be0318b94e88 drm/i915/execlists: Flush pending preemption events during reset
ac2854065991 drm/i915: Split execlists/guc reset preparations
f3b9334601ba drm/i915: Move engine reset prepare/finish to backends
75a82a377918 drm/i915/execlists: Refactor out complete_preempt_context()
20056e98212b drm/i915/selftests: Wait for idle between idle resets as well
3916a548bb30 drm/i915: Pack params to engine->schedule() into a struct
48d04c87b19e drm/i915: Check whitelist registers across resets

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2042/issues.html

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