[PATCH 3/3] Test

Yunwei Zhang yunwei.zhang at intel.com
Mon Apr 23 22:48:55 UTC 2018


Signed-off-by: Yunwei Zhang <yunwei.zhang at intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c   | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 44ca90a..48a23c1 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -776,6 +776,7 @@ static void sanitize_mcr(struct intel_device_info *info)
 	}
 
 	mcr = I915_READ(GEN8_MCR_SELECTOR);
+	DRM_WARN("mcr_sanitize: mcr_select = %x, mcr= %x", mcr_slice_subslice_select, mcr);
 	mcr &= ~mcr_slice_subslice_mask;
 
 	info->default_mcr_s_ss_select = 0;
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 2b24277..6c41133 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -834,8 +834,10 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 
 	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
 		      dev_priv->info.default_mcr_s_ss_select);
+	DRM_WARN("default = %08x, mcr_select= %08x", dev_priv->info.default_mcr_s_ss_select,mcr & mcr_slice_subslice_mask);
 	mcr &= ~mcr_slice_subslice_mask;
 	mcr |= mcr_slice_subslice_select;
+	DRM_WARN("AFTER: mcr_select= %x", mcr_slice_subslice_select);
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
-- 
2.7.4



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