[PATCH 25/25] wip: drm/i915/skl-: power down

[José Roberto de Souza]

---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 59 ++++++++++++++++++-------
 1 file changed, 43 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8ae497768c9b..4694b4aea95b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3667,6 +3667,34 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
 	cmn->ops->disable(dev_priv, cmn);
 }
 
+static void display_core_init(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
+
+	if (IS_IVYBRIDGE(dev_priv)) {
+		if (HAS_PCH_NOP(dev_priv)) {
+			u32 val = I915_READ(GEN7_MSG_CTL);
+
+			val &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+			I915_WRITE(GEN7_MSG_CTL, val);
+		}
+	} else if (INTEL_GEN(dev_priv) >= 7)
+		skl_pch_reset_handshake(dev_priv);
+
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
+	/* sync so it can take control of PW that BIOS enabled */
+	intel_power_domains_sync_hw(dev_priv);
+
+	mutex_lock(&power_domains->lock);
+
+	power_well_disable_all(dev_priv);
+
+	mutex_unlock(&power_domains->lock);
+}
+
 /**
  * intel_power_domains_init_hw - initialize hardware power domain state
  * @dev_priv: i915 device instance
@@ -3692,23 +3720,22 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 		skl_display_core_init(dev_priv, resume);
 	} else if (IS_GEN9_LP(dev_priv)) {
 		bxt_display_core_init(dev_priv, resume);
-	} else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
-		mutex_lock(&power_domains->lock);
-		chv_phy_control_init(dev_priv);
-		mutex_unlock(&power_domains->lock);
-	} else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
-		mutex_lock(&power_domains->lock);
-		vlv_cmnlane_wa(dev_priv);
-		mutex_unlock(&power_domains->lock);
-	} else if (IS_IVYBRIDGE(dev_priv)) {
-		if (HAS_PCH_NOP(dev_priv)) {
-			u32 val = I915_READ(GEN7_MSG_CTL);
-
-			val &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
-			I915_WRITE(GEN7_MSG_CTL, val);
+	} else if (IS_CHERRYVIEW(dev_priv)) {
+		if (INTEL_INFO(dev_priv)->num_pipes) {
+			mutex_lock(&power_domains->lock);
+			chv_phy_control_init(dev_priv);
+			mutex_unlock(&power_domains->lock);
 		}
-	} else if (INTEL_GEN(dev_priv) >= 7) {
-		skl_pch_reset_handshake(dev_priv);
+		display_core_init(dev_priv);
+	} else if (IS_VALLEYVIEW(dev_priv)) {
+		if (INTEL_INFO(dev_priv)->num_pipes) {
+			mutex_lock(&power_domains->lock);
+			vlv_cmnlane_wa(dev_priv);
+			mutex_unlock(&power_domains->lock);
+		}
+		display_core_init(dev_priv);
+	} else {
+		display_core_init(dev_priv);
 	}
 
 	/* For now, we need the power well to be always enabled. */
-- 
2.18.0