[PATCH 22/27] wip debug
José Roberto de Souza
jose.souza at intel.com
Tue Aug 7 17:58:40 UTC 2018
debug
debug: i915_power_domain_hw
debug
---
drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
drivers/gpu/drm/i915/intel_device_info.c | 8 ++++----
drivers/gpu/drm/i915/intel_fbdev.c | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++++++++++++++-
6 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f9ce35da4123..03dcd0d73c8d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2831,6 +2831,27 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused)
return 0;
}
+static int i915_power_domain_hw(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ int i;
+
+ mutex_lock(&power_domains->lock);
+ for (i = 0; i < power_domains->power_well_count; i++) {
+ struct i915_power_well *power_well;
+ bool enabled;
+
+ power_well = &power_domains->power_wells[i];
+ enabled = power_well->ops->is_enabled(dev_priv, power_well);
+ seq_printf(m, "%-25s hw enabled:%s\n", power_well->name,
+ yesno(enabled));
+ }
+ mutex_unlock(&power_domains->lock);
+
+ return 0;
+}
+
static int i915_power_domain_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4727,6 +4748,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_energy_uJ", i915_energy_uJ, 0},
{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
{"i915_power_domain_info", i915_power_domain_info, 0},
+ {"i915_power_domain_hw", i915_power_domain_hw, 0},
{"i915_dmc_info", i915_dmc_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_engine_info", i915_engine_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 97305e77d4b7..9f20784d668c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -878,6 +878,11 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
memcpy(device_info, match_info, sizeof(*device_info));
device_info->device_id = dev_priv->drm.pdev->device;
+ if (i915_modparams.disable_display) {
+ DRM_DEBUG_KMS("Setting num_pipes=0 as display is disabled\n");
+ device_info->num_pipes = 0;
+ }
+
BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
sizeof(device_info->platform_mask) * BITS_PER_BYTE);
BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0ef0c6448d53..81c613ca44d9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -776,10 +776,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
info->num_sprites[pipe] = 1;
}
- if (i915_modparams.disable_display) {
- DRM_INFO("Display disabled (module parameter)\n");
- info->num_pipes = 0;
- } else if (info->num_pipes > 0 &&
+
+ if (info->num_pipes > 0 &&
(IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
@@ -835,6 +833,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
disabled_mask);
else
info->num_pipes -= num_bits;
+ } else {
+ DRM_DEBUG_KMS("else in intel_device_info_runtime_init() info->num_pipes=%d\n", info->num_pipes);
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index fb2f9fce34cd..1e7ce44c8979 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -183,6 +183,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
void __iomem *vaddr;
int ret;
+ WARN_ON(!INTEL_INFO(dev_priv)->num_pipes);
+
if (intel_fb &&
(sizes->fb_width > intel_fb->base.width ||
sizes->fb_height > intel_fb->base.height)) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0ab10a974850..ecfd8b3700eb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9315,6 +9315,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN5(dev_priv))
i915_ironlake_get_mem_freq(dev_priv);
+ // this stuff makes sense here?
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6705ad7a0a2b..8ae497768c9b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -270,6 +270,9 @@ bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
void intel_display_set_init_power(struct drm_i915_private *dev_priv,
bool enable)
{
+ //DRM_DEBUG_KMS("intel_display_set_init_power() enable=%d init_power_on=%d\n", enable, dev_priv->power_domains.init_power_on);
+ //dump_stack();
+
if (dev_priv->power_domains.init_power_on == enable)
return;
@@ -974,7 +977,7 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
I915_WRITE(CBR1_VLV, 0);
- WARN_ON(dev_priv->rawclk_freq == 0);
+ WARN_ON(INTEL_INFO(dev_priv)->num_pipes && dev_priv->rawclk_freq == 0);
I915_WRITE(RAWCLK_FREQ_VLV,
DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
@@ -985,6 +988,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
struct intel_encoder *encoder;
enum pipe pipe;
+ // TODO no need to run that
+
+ WARN_ON(!INTEL_INFO(dev_priv)->num_pipes);
+
/*
* Enable the CRI clock source so we can get at the
* display and the reference clock for VGA
@@ -1638,6 +1645,8 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
if (domain == POWER_DOMAIN_INIT && !INTEL_INFO(dev_priv)->num_pipes)
goto end;
+ DRM_DEBUG_KMS("intel_display_power_put() domain=%d\n", domain);
+
power_domains = &dev_priv->power_domains;
mutex_lock(&power_domains->lock);
@@ -2948,11 +2957,16 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *power_well;
+ DRM_DEBUG_KMS("intel_power_domains_sync_hw\n");
+
mutex_lock(&power_domains->lock);
for_each_power_well(dev_priv, power_well) {
power_well->ops->sync_hw(dev_priv, power_well);
power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
power_well);
+ if (power_well->hw_enabled) {
+ DRM_DEBUG_KMS("\tpw %s hw enabled\n", power_well->name);
+ }
}
mutex_unlock(&power_domains->lock);
}
--
2.18.0
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