[PATCH 3/3] drm/i915: Simplify enabling gen6/7 user interrupts

Chris Wilson chris at chris-wilson.co.uk
Wed Aug 8 09:42:25 UTC 2018


As gen6 introduced per-engine masking of the user interrupt at source,
we can leave the global GT interrupt unmasked (as we can filter the
interrupts earlier) and so reduce enabling/disabling the user interrupt
to a single register write in the local engine.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala at intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         | 14 +++++++-------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ----------------------
 2 files changed, 7 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..fb83198d0c8d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3995,19 +3995,19 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
 
 	pm_irqs = gt_irqs = 0;
 
-	dev_priv->gt_irq_mask = ~0;
 	if (HAS_L3_DPF(dev_priv)) {
-		/* L3 parity interrupt is always unmasked. */
-		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
 		gt_irqs |= GT_PARITY_ERROR(dev_priv);
 	}
 
 	gt_irqs |= GT_RENDER_USER_INTERRUPT;
-	if (IS_GEN5(dev_priv)) {
+	if (IS_GEN5(dev_priv))
 		gt_irqs |= ILK_BSD_USER_INTERRUPT;
-	} else {
+	else
 		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
-	}
+
+	dev_priv->gt_irq_mask = ~0u;
+	if (INTEL_GEN(dev_priv) >= 6)
+		dev_priv->gt_irq_mask = ~gt_irqs;
 
 	GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
 
@@ -4021,7 +4021,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
 			dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
 		}
 
-		dev_priv->pm_imr = 0xffffffff;
+		dev_priv->pm_imr = ~pm_irqs;
 		GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
 	}
 }
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b65cf7832b39..4747c8490cd0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -882,7 +882,6 @@ gen6_irq_enable(struct intel_engine_cs *engine)
 	I915_WRITE_IMR(engine,
 		       ~(engine->irq_enable_mask |
 			 engine->irq_keep_mask));
-	gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 }
 
 static void
@@ -891,25 +890,6 @@ gen6_irq_disable(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 
 	I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
-	gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
-}
-
-static void
-hsw_vebox_irq_enable(struct intel_engine_cs *engine)
-{
-	struct drm_i915_private *dev_priv = engine->i915;
-
-	I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
-	gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
-}
-
-static void
-hsw_vebox_irq_disable(struct intel_engine_cs *engine)
-{
-	struct drm_i915_private *dev_priv = engine->i915;
-
-	I915_WRITE_IMR(engine, ~0);
-	gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
 }
 
 static int
@@ -2271,8 +2251,6 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
 
 	engine->emit_flush = gen6_ring_flush;
 	engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
-	engine->irq_enable = hsw_vebox_irq_enable;
-	engine->irq_disable = hsw_vebox_irq_disable;
 
 	return intel_init_ring_buffer(engine);
 }
-- 
2.18.0



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