[PATCH 6/6] markup

Chris Wilson chris at chris-wilson.co.uk
Thu Aug 9 17:59:29 UTC 2018 

---
 drivers/gpu/drm/i915/gvt/mmio_context.c       |  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c           | 48 +++++++++----------
 drivers/gpu/drm/i915/i915_drv.c               |  2 +-
 drivers/gpu/drm/i915/i915_gem.c               | 20 ++++----
 drivers/gpu/drm/i915/i915_gem_fence_reg.c     |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  8 ++--
 drivers/gpu/drm/i915/i915_gem_shrinker.c      |  8 ++--
 drivers/gpu/drm/i915/i915_irq.c               |  2 +-
 drivers/gpu/drm/i915/i915_pmu.c               |  6 +--
 drivers/gpu/drm/i915/i915_sysfs.c             |  8 ++--
 drivers/gpu/drm/i915/intel_display.c          |  2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c        |  4 +-
 drivers/gpu/drm/i915/intel_fbdev.c            |  2 +-
 drivers/gpu/drm/i915/intel_guc_log.c          |  6 +--
 drivers/gpu/drm/i915/intel_hotplug.c          |  2 +-
 drivers/gpu/drm/i915/intel_panel.c            |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c           |  2 +-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  2 +-
 .../gpu/drm/i915/selftests/i915_gem_context.c |  4 +-
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  8 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
 .../gpu/drm/i915/selftests/i915_gem_object.c  |  6 +--
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |  2 +-
 23 files changed, 77 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 42e1e6bdcc2c..e1fdc56a67c1 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -562,7 +562,7 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
 	 * performace for batch mmio read/write, so we need
 	 * handle forcewake mannually.
 	 */
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 	switch_mmio(pre, next, ring_id);
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 23f38bc257a2..fdd9f4a78ae0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -706,7 +706,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 	enum intel_engine_id id;
 	int i, pipe;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	if (IS_CHERRYVIEW(dev_priv)) {
 		seq_printf(m, "Master Interrupt Control:\t%08x\n",
@@ -981,7 +981,7 @@ static int i915_gpu_info_open(struct inode *inode, struct file *file)
 	struct drm_i915_private *i915 = inode->i_private;
 	struct i915_gpu_state *gpu;
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	gpu = i915_capture_gpu_state(i915);
 	intel_runtime_pm_put(i915);
 	if (!gpu)
@@ -1043,7 +1043,7 @@ i915_next_seqno_set(void *data, u64 val)
 	if (ret)
 		return ret;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	ret = i915_gem_set_global_seqno(dev, val);
 	intel_runtime_pm_put(dev_priv);
 
@@ -1062,7 +1062,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 	int ret = 0;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	if (IS_GEN5(dev_priv)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
@@ -1331,7 +1331,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
 		return 0;
 	}
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	for_each_engine(engine, dev_priv, id) {
 		acthd[id] = intel_engine_get_active_head(engine);
@@ -1618,7 +1618,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	int err;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		err = vlv_drpc_info(m);
@@ -1653,7 +1653,7 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
 	if (!HAS_FBC(dev_priv))
 		return -ENODEV;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	mutex_lock(&fbc->lock);
 
 	if (intel_fbc_is_active(dev_priv))
@@ -1729,7 +1729,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
 	if (!HAS_IPS(dev_priv))
 		return -ENODEV;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	seq_printf(m, "Enabled by kernel parameter: %s\n",
 		   yesno(i915_modparams.enable_ips));
@@ -1753,7 +1753,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	bool sr_enabled = false;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
 	if (INTEL_GEN(dev_priv) >= 9)
@@ -1816,7 +1816,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	if (!HAS_LLC(dev_priv))
 		return -ENODEV;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
 	if (ret)
@@ -2020,7 +2020,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
 		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));
@@ -2151,7 +2151,7 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
 	if (ret)
 		goto out_unlock;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	if (INTEL_GEN(dev_priv) >= 8)
 		gen8_ppgtt_info(m, dev_priv);
@@ -2301,7 +2301,7 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data)
 	p = drm_seq_file_printer(m);
 	intel_uc_fw_dump(&dev_priv->huc.fw, &p);
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
 	intel_runtime_pm_put(dev_priv);
 
@@ -2320,7 +2320,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
 	p = drm_seq_file_printer(m);
 	intel_uc_fw_dump(&dev_priv->guc.fw, &p);
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	tmp = I915_READ(GUC_STATUS);
 
@@ -2705,7 +2705,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	if (!sink_support)
 		return 0;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	mutex_lock(&dev_priv->psr.lock);
 	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
@@ -2756,7 +2756,7 @@ i915_edp_psr_debug_set(void *data, u64 val)
 
 	DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	intel_psr_irq_control(dev_priv, !!val);
 	intel_runtime_pm_put(dev_priv);
 
@@ -2788,7 +2788,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data)
 	if (INTEL_GEN(dev_priv) < 6)
 		return -ENODEV;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
 		intel_runtime_pm_put(dev_priv);
@@ -2869,7 +2869,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
 	csr = &dev_priv->csr;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
 	seq_printf(m, "path: %s\n", csr->fw_path);
@@ -3186,7 +3186,7 @@ static int i915_display_info(struct seq_file *m, void *unused)
 	struct drm_connector *connector;
 	struct drm_connector_list_iter conn_iter;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	seq_printf(m, "CRTC info\n");
 	seq_printf(m, "---------\n");
 	for_each_intel_crtc(dev, crtc) {
@@ -3246,7 +3246,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
 	enum intel_engine_id id;
 	struct drm_printer p;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	seq_printf(m, "GT awake? %s (epoch %u)\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.epoch);
@@ -3377,7 +3377,7 @@ static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
 	if (ret < 0)
 		return ret;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	if (!dev_priv->ipc_enabled && enable)
 		DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
 	dev_priv->wm.distrust_bios_wm = true;
@@ -4196,7 +4196,7 @@ i915_cache_sharing_get(void *data, u64 *val)
 	if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
 		return -ENODEV;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
 
@@ -4219,7 +4219,7 @@ i915_cache_sharing_set(void *data, u64 val)
 	if (val > 3)
 		return -EINVAL;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
 
 	/* Update the cache sharing policy here as well */
@@ -4464,7 +4464,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 	sseu.max_eus_per_subslice =
 		INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_sseu_device_status(dev_priv, &sseu);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b6e83043ac9d..c1c899c2b63f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1387,7 +1387,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (ret < 0)
 		goto out_pci_disable;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	ret = i915_driver_init_mmio(dev_priv);
 	if (ret < 0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 71502512ac1f..bd93194e40e0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -205,7 +205,7 @@ void i915_gem_unpark(struct drm_i915_private *i915)
 	if (i915->gt.awake)
 		return;
 
-	intel_runtime_pm_get_noresume(i915);
+	__intel_runtime_pm_get_noresume(i915, true);
 
 	/*
 	 * It seems that the DMC likes to transition between the DC states a lot
@@ -809,7 +809,7 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
 
 	i915_gem_chipset_flush(dev_priv);
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	spin_lock_irq(&dev_priv->uncore.lock);
 
 	POSTING_READ_FW(RING_HEAD(RENDER_RING_BASE));
@@ -1188,7 +1188,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
 	if (ret)
 		return ret;
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
 				       PIN_MAPPABLE |
 				       PIN_NONFAULT |
@@ -1381,13 +1381,13 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
 		 * This easily dwarfs any performance advantage from
 		 * using the cache bypass of indirect GGTT access.
 		 */
-		if (!intel_runtime_pm_get_if_in_use(i915)) {
+		if (!__intel_runtime_pm_get_if_in_use(i915, true)) {
 			ret = -EFAULT;
 			goto out_unlock;
 		}
 	} else {
 		/* No backing pages, no fallback, we must force GGTT access */
-		intel_runtime_pm_get(i915);
+		__intel_runtime_pm_get(i915, true);
 	}
 
 	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
@@ -2048,7 +2048,7 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
 	if (ret)
 		goto err;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	ret = i915_mutex_lock_interruptible(dev);
 	if (ret)
@@ -2209,7 +2209,7 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj)
 	 * wakeref.
 	 */
 	lockdep_assert_held(&i915->drm.struct_mutex);
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 
 	if (!obj->userfault_count)
 		goto out;
@@ -4850,7 +4850,7 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915,
 {
 	struct drm_i915_gem_object *obj, *on;
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	llist_for_each_entry_safe(obj, on, freed, freed) {
 		struct i915_vma *vma, *vn;
 
@@ -5019,7 +5019,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 
 	mutex_lock(&i915->drm.struct_mutex);
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
 
 	/*
@@ -5058,7 +5058,7 @@ int i915_gem_suspend(struct drm_i915_private *i915)
 
 	GEM_TRACE("\n");
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	intel_suspend_gt_powersave(i915);
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index d548ac05ccd7..228b09214af1 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -257,7 +257,7 @@ static int fence_update(struct drm_i915_fence_reg *fence,
 	 * If the device is currently powered down, we will defer the write
 	 * to the runtime resume, see i915_gem_restore_fences().
 	 */
-	if (intel_runtime_pm_get_if_in_use(fence->i915)) {
+	if (__intel_runtime_pm_get_if_in_use(fence->i915, true)) {
 		fence_write(fence, vma);
 		intel_runtime_pm_put(fence->i915);
 	}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4137af4bd8f5..76133027312e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2725,7 +2725,7 @@ static int ggtt_bind_vma(struct i915_vma *vma,
 	if (i915_gem_object_is_readonly(obj))
 		pte_flags |= PTE_READ_ONLY;
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
 	intel_runtime_pm_put(i915);
 
@@ -2745,7 +2745,7 @@ static void ggtt_unbind_vma(struct i915_vma *vma)
 {
 	struct drm_i915_private *i915 = vma->vm->i915;
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
 	intel_runtime_pm_put(i915);
 }
@@ -2779,7 +2779,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
 	}
 
 	if (flags & I915_VMA_GLOBAL_BIND) {
-		intel_runtime_pm_get(i915);
+		__intel_runtime_pm_get(i915, true);
 		vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
 		intel_runtime_pm_put(i915);
 	}
@@ -2792,7 +2792,7 @@ static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
 	struct drm_i915_private *i915 = vma->vm->i915;
 
 	if (vma->flags & I915_VMA_GLOBAL_BIND) {
-		intel_runtime_pm_get(i915);
+		__intel_runtime_pm_get(i915, true);
 		vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
 		intel_runtime_pm_put(i915);
 	}
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index ea90d3a0d511..70d7f64762a5 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -186,7 +186,7 @@ i915_gem_shrink(struct drm_i915_private *i915,
 	 * we will force the wake during oom-notifier.
 	 */
 	if ((flags & I915_SHRINK_BOUND) &&
-	    !intel_runtime_pm_get_if_in_use(i915))
+	    !__intel_runtime_pm_get_if_in_use(i915, true))
 		flags &= ~I915_SHRINK_BOUND;
 
 	/*
@@ -297,7 +297,7 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private *i915)
 {
 	unsigned long freed;
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	freed = i915_gem_shrink(i915, -1UL, NULL,
 				I915_SHRINK_BOUND |
 				I915_SHRINK_UNBOUND |
@@ -373,7 +373,7 @@ i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
 					 I915_SHRINK_BOUND |
 					 I915_SHRINK_UNBOUND);
 	if (sc->nr_scanned < sc->nr_to_scan && current_is_kswapd()) {
-		intel_runtime_pm_get(i915);
+		__intel_runtime_pm_get(i915, true);
 		freed += i915_gem_shrink(i915,
 					 sc->nr_to_scan - sc->nr_scanned,
 					 &sc->nr_scanned,
@@ -476,7 +476,7 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr
 	if (ret)
 		goto out;
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	freed_pages += i915_gem_shrink(i915, -1UL, NULL,
 				       I915_SHRINK_BOUND |
 				       I915_SHRINK_UNBOUND |
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..d62cd3da5cd2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3280,7 +3280,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
 	 * isn't the case at least when we get here by doing a
 	 * simulated reset via debugfs, so get an RPM reference.
 	 */
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
 
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index c39541ed2219..563a8d87ff4f 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -174,7 +174,7 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
 	if (!dev_priv->gt.awake)
 		return;
 
-	if (!intel_runtime_pm_get_if_in_use(dev_priv))
+	if (!__intel_runtime_pm_get_if_in_use(dev_priv, true))
 		return;
 
 	for_each_engine(engine, dev_priv, id) {
@@ -227,7 +227,7 @@ frequency_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
 
 		val = dev_priv->gt_pm.rps.cur_freq;
 		if (dev_priv->gt.awake &&
-		    intel_runtime_pm_get_if_in_use(dev_priv)) {
+		    __intel_runtime_pm_get_if_in_use(dev_priv, true)) {
 			val = intel_get_cagf(dev_priv,
 					     I915_READ_NOTRACE(GEN6_RPSTAT1));
 			intel_runtime_pm_put(dev_priv);
@@ -445,7 +445,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
 	unsigned long flags;
 	u64 val;
 
-	if (intel_runtime_pm_get_if_in_use(i915)) {
+	if (__intel_runtime_pm_get_if_in_use(i915, true)) {
 		val = __get_rc6(i915);
 		intel_runtime_pm_put(i915);
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index e5e6f6bb2b05..c57b1b9c9906 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -44,7 +44,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
 {
 	u64 res;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	res = intel_rc6_residency_us(dev_priv, reg);
 	intel_runtime_pm_put(dev_priv);
 
@@ -260,7 +260,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 	int ret;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	mutex_lock(&dev_priv->pcu_lock);
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -361,7 +361,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 	if (ret)
 		return ret;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	mutex_lock(&dev_priv->pcu_lock);
 
@@ -419,7 +419,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 	if (ret)
 		return ret;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	mutex_lock(&dev_priv->pcu_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 53e7a7e75384..cb4dc6dd970b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2112,7 +2112,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
 	 * intel_runtime_pm_put(), so it is correct to wrap only the
 	 * pin/unpin/fence and not more.
 	 */
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 99d5a24219c1..17ac44f4112c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -935,7 +935,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
 	bool idle = true;
 
 	/* If the whole device is asleep, the engine must be idle */
-	if (!intel_runtime_pm_get_if_in_use(dev_priv))
+	if (!__intel_runtime_pm_get_if_in_use(dev_priv, true))
 		return true;
 
 	/* First check that no commands are left in the ring */
@@ -1498,7 +1498,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
 
 	rcu_read_unlock();
 
-	if (intel_runtime_pm_get_if_in_use(engine->i915)) {
+	if (__intel_runtime_pm_get_if_in_use(engine->i915, true)) {
 		intel_engine_print_registers(engine, m);
 		intel_runtime_pm_put(engine->i915);
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index fb2f9fce34cd..357a6b320324 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -207,7 +207,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
 	}
 
 	mutex_lock(&dev->struct_mutex);
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	/* Pin the GGTT vma for our access via info->screen_base.
 	 * This also validates that any existing fb inherited from the
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index d3ebdbc0182e..086f003811f4 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -443,7 +443,7 @@ static void guc_log_capture_logs(struct intel_guc_log *log)
 	 * Generally device is expected to be active only at this
 	 * time, so get/put should be really quick.
 	 */
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	guc_action_flush_log_complete(guc);
 	intel_runtime_pm_put(dev_priv);
 }
@@ -524,7 +524,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
 		goto out_unlock;
 	}
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	ret = guc_action_control_log(guc, GUC_LOG_LEVEL_IS_VERBOSE(level),
 				     GUC_LOG_LEVEL_IS_ENABLED(level),
 				     GUC_LOG_LEVEL_TO_VERBOSITY(level));
@@ -608,7 +608,7 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
 	 */
 	flush_work(&log->relay.flush_work);
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	guc_action_flush_log(guc);
 	intel_runtime_pm_put(i915);
 
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 648a13c6043c..342175aa76e4 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -212,7 +212,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
 	struct drm_device *dev = &dev_priv->drm;
 	enum hpd_pin pin;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	spin_lock_irq(&dev_priv->irq_lock);
 	for_each_hpd_pin(pin) {
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 4a9f139e7b73..53f385c02628 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1206,7 +1206,7 @@ static int intel_backlight_device_get_brightness(struct backlight_device *bd)
 	u32 hw_level;
 	int ret;
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 
 	hw_level = intel_panel_get_backlight(connector);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c2fcb51fc58a..42c1892117b9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1695,7 +1695,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
 
 	flags = reg->offset & (entry->size - 1);
 
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 	if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
 		reg->val = I915_READ64_2x32(entry->offset_ldw,
 					    entry->offset_udw);
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index e272127783fe..64a4bf3f9c8f 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1764,7 +1764,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv)
 		return PTR_ERR(file);
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
-	intel_runtime_pm_get(dev_priv);
+	__intel_runtime_pm_get(dev_priv, true);
 
 	ctx = live_context(dev_priv, file);
 	if (IS_ERR(ctx)) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 1c92560d35da..3a99ceae3abc 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -390,7 +390,7 @@ static int igt_ctx_exec(void *arg)
 				}
 			}
 
-			intel_runtime_pm_get(i915);
+			__intel_runtime_pm_get(i915, true);
 			err = gpu_fill(obj, ctx, engine, dw);
 			intel_runtime_pm_put(i915);
 			if (err) {
@@ -491,7 +491,7 @@ static int igt_ctx_readonly(void *arg)
 					i915_gem_object_set_readonly(obj);
 			}
 
-			intel_runtime_pm_get(i915);
+			__intel_runtime_pm_get(i915, true);
 			err = gpu_fill(obj, ctx, engine, dw);
 			intel_runtime_pm_put(i915);
 			if (err) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 128ad1cf0647..f5477dc69ffd 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -355,7 +355,7 @@ static int igt_evict_contexts(void *arg)
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 
 	/* Reserve a block so that we know we have enough to fit a few rq */
 	memset(&hole, 0, sizeof(hole));
@@ -400,8 +400,10 @@ static int igt_evict_contexts(void *arg)
 		struct drm_file *file;
 
 		file = mock_file(i915);
-		if (IS_ERR(file))
-			return PTR_ERR(file);
+		if (IS_ERR(file)) {
+			err = PTR_ERR(file);
+			break;
+		}
 
 		count = 0;
 		mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 8e2e269db97e..3630a971ce9d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -293,7 +293,7 @@ static int lowlevel_hole(struct drm_i915_private *i915,
 			mock_vma.node.size = BIT_ULL(size);
 			mock_vma.node.start = addr;
 
-			intel_runtime_pm_get(i915);
+			__intel_runtime_pm_get(i915, true);
 			vm->insert_entries(vm, &mock_vma, I915_CACHE_NONE, 0);
 			intel_runtime_pm_put(i915);
 		}
@@ -1169,7 +1169,7 @@ static int igt_ggtt_page(void *arg)
 	if (err)
 		goto out_unpin;
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 
 	for (n = 0; n < count; n++) {
 		u64 offset = tmp.start + n * PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index 6d3516d5bff9..ff90654f416e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -332,7 +332,7 @@ static int igt_partial_tiling(void *arg)
 	}
 
 	mutex_lock(&i915->drm.struct_mutex);
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 
 	if (1) {
 		IGT_TIMEOUT(end);
@@ -503,7 +503,7 @@ static void disable_retire_worker(struct drm_i915_private *i915)
 {
 	mutex_lock(&i915->drm.struct_mutex);
 	if (!i915->gt.active_requests++) {
-		intel_runtime_pm_get(i915);
+		__intel_runtime_pm_get(i915, true);
 		i915_gem_unpark(i915);
 		intel_runtime_pm_put(i915);
 	}
@@ -585,7 +585,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
 		}
 
 		mutex_lock(&i915->drm.struct_mutex);
-		intel_runtime_pm_get(i915);
+		__intel_runtime_pm_get(i915, true);
 		err = make_obj_busy(obj);
 		intel_runtime_pm_put(i915);
 		mutex_unlock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index db378226ac10..c40ecdd9e4db 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -1497,7 +1497,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
 	if (i915_terminally_wedged(&i915->gpu_error))
 		return -EIO; /* we're long past hope of a successful reset */
 
-	intel_runtime_pm_get(i915);
+	__intel_runtime_pm_get(i915, true);
 	saved_hangcheck = fetch_and_zero(&i915_modparams.enable_hangcheck);
 
 	err = i915_subtests(tests, i915);
-- 
2.18.0

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