[PATCH 4/4] init-power

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_drv.c      | 25 ++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_display.c | 20 --------------------
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_pm.c      | 11 +++++++++++
 4 files changed, 30 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index eb6e2107b5b6..2d49893d3047 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -664,13 +664,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	if (ret)
 		goto cleanup_vga_client;
 
-	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
-	intel_update_rawclk(dev_priv);
-
-	intel_power_domains_init_hw(dev_priv, false);
-
-	intel_csr_ucode_init(dev_priv);
-
 	ret = intel_irq_install(dev_priv);
 	if (ret)
 		goto cleanup_csr;
@@ -921,6 +914,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 	intel_init_audio_hooks(dev_priv);
 	intel_display_crc_init(dev_priv);
 
+	drm_mode_config_init(&dev_priv->drm);
+
 	intel_detect_preproduction_hw(dev_priv);
 
 	return 0;
@@ -1404,7 +1399,20 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 			goto out_cleanup_hw;
 	}
 
+	intel_csr_ucode_init(dev_priv);
+
+	intel_update_czclk(dev_priv);
+	intel_update_max_cdclk(dev_priv);
+	intel_update_rawclk(dev_priv);
+
+	intel_power_domains_init_hw(dev_priv, false);
+
 	ret = i915_load_modeset_init(&dev_priv->drm);
+
+	/* intel_power_domains_init_hw() counter part  */
+	intel_display_set_init_power(dev_priv, false);
+	intel_power_domains_verify_state(dev_priv);
+
 	if (ret < 0)
 		goto out_cleanup_hw;
 
@@ -1777,6 +1785,9 @@ static int i915_drm_resume(struct drm_device *dev)
 
 	intel_opregion_notify_adapter(dev_priv, PCI_D0);
 
+	intel_display_set_init_power(dev_priv, false);
+	intel_power_domains_verify_state(dev_priv);
+
 	enable_rpm_wakeref_asserts(dev_priv);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cc3f21ddae9c..74824ac25a91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -218,17 +218,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 				 dev_priv->hpll_freq);
 }
 
-static void intel_update_czclk(struct drm_i915_private *dev_priv)
-{
-	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
-		return;
-
-	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
-						      CCK_CZ_CLOCK_CONTROL);
-
-	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
-}
-
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 		    const struct intel_crtc_state *pipe_config)
@@ -15186,8 +15175,6 @@ int intel_modeset_init(struct drm_device *dev)
 
 	dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
 
-	drm_mode_config_init(dev);
-
 	dev->mode_config.min_width = 0;
 	dev->mode_config.min_height = 0;
 
@@ -15267,12 +15254,8 @@ int intel_modeset_init(struct drm_device *dev)
 	intel_shared_dpll_init(dev);
 	intel_update_fdi_pll_freq(dev_priv);
 
-	intel_update_czclk(dev_priv);
 	intel_modeset_init_hw(dev);
 
-	if (dev_priv->max_cdclk_freq == 0)
-		intel_update_max_cdclk(dev_priv);
-
 	/* Just disable it once at startup */
 	i915_disable_vga(dev_priv);
 	intel_setup_outputs(dev_priv);
@@ -15900,9 +15883,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 		if (WARN_ON(put_domains))
 			modeset_put_power_domains(dev_priv, put_domains);
 	}
-	intel_display_set_init_power(dev_priv, false);
-
-	intel_power_domains_verify_state(dev_priv);
 
 	intel_fbc_init_pipe_state(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 364fc2504fa4..dc1714a5aa3b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2046,6 +2046,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 
 
 /* intel_pm.c */
+void intel_update_czclk(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
 void intel_suspend_hw(struct drm_i915_private *dev_priv);
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e297791c6846..359a07f43614 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9296,6 +9296,17 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 	}
 }
 
+void intel_update_czclk(struct drm_i915_private *dev_priv)
+{
+	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
+		return;
+
+	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
+						      CCK_CZ_CLOCK_CONTROL);
+
+	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
+}
+
 /* Set up chip specific power management-related functions */
 void intel_init_pm(struct drm_i915_private *dev_priv)
 {
-- 
2.18.0