[PATCH] drm/i915/execlists: Clear STOP_RING bit before restoring the context

[Chris Wilson]

Before a reset, we set the STOP_RING bit of RING_MI_MODE to freeze the
engine. However, sometimes we observe that upon restart, the engine
freezes again with the STOP_RING bit still asserted. By inspection, we
know that the register itself is cleared by the GPU reset, so that bit
must be preserved inside the context image and reloaded from there. A
simple fix (as the RING_MI_MODE is at a fixed offset in a valid context)
is to clobber the STOP_RING bit inside the image before the initial
execution of an idle context.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Cc: Michel Thierry <michel.thierry at intel.com>
Cc: Michał Winiarski <michal.winiarski at intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c     | 9 +++++++++
 drivers/gpu/drm/i915/intel_lrc_reg.h | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3f90c74038ef..bb7d40127cb9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1338,6 +1338,15 @@ __execlists_context_pin(struct intel_engine_cs *engine,
 	GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
 	ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
 
+	/*
+	 * After a reset, the context may have preserved the STOP bit
+	 * of RING_MI_MODE we used to freeze the active engine before the
+	 * reset. If that bit is restored the ring stops instead of being
+	 * executed.
+	 */
+	ce->lrc_reg_state[CTX_MI_MODE + 1] |= STOP_RING << 16;
+	ce->lrc_reg_state[CTX_MI_MODE + 1] &= ~STOP_RING;
+
 	ce->state->obj->pin_global++;
 	i915_gem_context_get(ctx);
 	return ce;
diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h b/drivers/gpu/drm/i915/intel_lrc_reg.h
index 5ef932d810a7..3b155ecbfa92 100644
--- a/drivers/gpu/drm/i915/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/intel_lrc_reg.h
@@ -39,6 +39,8 @@
 #define CTX_R_PWR_CLK_STATE		0x42
 #define CTX_END				0x44
 
+#define CTX_MI_MODE			0x54
+
 #define CTX_REG(reg_state, pos, reg, val) do { \
 	u32 *reg_state__ = (reg_state); \
 	const u32 pos__ = (pos); \
-- 
2.18.0