[PATCH 14/19] drm/i915/guc: New engine-reset-complete message

[Michal Wajdeczko]

GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer
to earlier ENGINE_RESET request from the host. Once this message
is received, clear engine reset flag to unblock our reset process.

Credits-to: Michel Thierry <michel.thierry at intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Michel Thierry <michel.thierry at intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
Cc: Michal Winiarski <michal.winiarski at intel.com>
Cc: Tomasz Lis <tomasz.lis at intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c      | 52 +++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_guc.h      |  3 +-
 drivers/gpu/drm/i915/intel_guc_ct.c   |  2 +-
 drivers/gpu/drm/i915/intel_guc_fwif.h |  3 +-
 4 files changed, 46 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 64f1dca..2985f05 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -511,17 +511,7 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc)
 	spin_unlock(&guc->irq_lock);
 	enable_rpm_wakeref_asserts(dev_priv);
 
-	intel_guc_to_host_process_recv_msg(guc, msg);
-}
-
-void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg)
-{
-	/* Make sure to handle only enabled messages */
-	msg &= guc->msg_enabled_mask;
-
-	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
-		   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
-		intel_guc_log_handle_flush_event(&guc->log);
+	intel_guc_to_host_process_recv_msg(guc, &msg, 1);
 }
 
 int intel_guc_sample_forcewake(struct intel_guc *guc)
@@ -581,6 +571,7 @@ int intel_guc_suspend(struct intel_guc *guc)
 {
 	GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES);
 	bitmap32_set_bit(&guc->engine_class_under_reset, guc_class);
+	intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE);
 }
 
 static inline void
@@ -588,6 +579,7 @@ int intel_guc_suspend(struct intel_guc *guc)
 {
 	GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES);
 	bitmap32_clear_bit(&guc->engine_class_under_reset, guc_class);
+	intel_guc_disable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE);
 }
 
 static inline bool
@@ -652,6 +644,24 @@ int intel_guc_reset_engine(struct intel_guc *guc,
 	return ret;
 }
 
+/*
+ * GuC notifies host that reset engine has completed.
+ * This message should only be received after a request-reset h2g,
+ * so check that and clear the engine_class_under_reset flag.
+ */
+static void guc_handle_engine_reset_completed(struct intel_guc *guc,
+					      const u32 engine_class)
+{
+	if (engine_class >= GUC_MAX_ENGINE_CLASSES ||
+	    !guc_is_class_under_reset(guc, engine_class)) {
+		DRM_WARN("Unexpected reset-complete for engine class: %d",
+			 engine_class);
+		return;
+	}
+
+	guc_clear_class_under_reset(guc, engine_class);
+}
+
 /**
  * intel_guc_resume() - notify GuC resuming from suspend state
  * @guc:	the guc
@@ -754,3 +764,23 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
 {
 	return guc_to_i915(guc)->wopcm.guc.size;
 }
+
+void intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
+					const u32 *payload, u32 len)
+{
+	u32 msg;
+
+	GEM_BUG_ON(!len);
+
+	/* Make sure to handle only enabled messages */
+	msg = payload[0] & guc->msg_enabled_mask;
+
+	if (msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
+		   INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER))
+		intel_guc_log_handle_flush_event(&guc->log);
+
+	if (msg & INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE) {
+		GEM_BUG_ON(len != 3);
+		guc_handle_engine_reset_completed(guc, payload[1]);
+	}
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 88ce56f..48d221f 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -176,7 +176,8 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
 void intel_guc_to_host_event_handler(struct intel_guc *guc);
 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
 void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc);
-void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg);
+void intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
+					const u32 *payload, u32 len);
 int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 int intel_guc_suspend(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index a52883e..0adc63f 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -716,7 +716,7 @@ static void ct_process_request(struct intel_guc_ct *ct,
 	case INTEL_GUC_ACTION_DEFAULT:
 		if (unlikely(len < 1))
 			goto fail_unexpected;
-		intel_guc_to_host_process_recv_msg(guc, *payload);
+		intel_guc_to_host_process_recv_msg(guc, payload, len);
 		break;
 
 	default:
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 156db08..1958581 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -757,7 +757,8 @@ enum intel_guc_response_status {
 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
 enum intel_guc_recv_message {
 	INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
-	INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
+	INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3),
+	INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE = BIT(25),
 };
 
 #endif
-- 
1.9.1