[PATCH 1/2] drm/i915: Rename full ppgtt configuration to be more generic

Bob Paauwe bob.j.paauwe at intel.com
Wed Aug 22 16:29:59 UTC 2018


For ppgtt, what we're really interested in is the number of page
walk levels for each platform. Rename the device info fields to
reflect this:

.has_full_48b_ppgtt  -> .has_full_4lvl_ppgtt
.has_full_ppgtt	     -> .has_full_3lvl_ppgtt

Then add a new field, full_ppgtt_bits, that defines the actual
address range.  This gives us more flexibility and will work for
cases where we have platforms with different address ranges but
share the same page walk levels.

Since GEN9, ppgtt is now required to be enabled so it no longer makes
sense to override it.  We now ignore the module parameter and rely
only on the platform/device configuration to properly setup ppgtt.

Signed-off-by: Bob Paauwe <bob.j.paauwe at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            |  6 +++---
 drivers/gpu/drm/i915/i915_gem_context.c    |  2 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 17 +++++++++--------
 drivers/gpu/drm/i915/i915_pci.c            | 18 +++++++++++-------
 drivers/gpu/drm/i915/intel_device_info.h   |  7 +++++--
 6 files changed, 30 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c77139..51a7e234f917 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2568,9 +2568,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
-#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
+#define USES_PPGTT(dev_priv)		((dev_priv)->info.has_aliasing_ppgtt)
+#define USES_FULL_3LVL_PPGTT(dev_priv)	((dev_priv)->info.has_full_3lvl_ppgtt)
+#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.has_full_4lvl_ppgtt)
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
 	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..e2078dd8116e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -361,7 +361,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (USES_FULL_PPGTT(dev_priv)) {
+	if (USES_FULL_3LVL_PPGTT(dev_priv) || USES_FULL_4LVL_PPGTT(dev_priv)) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a926d7d47183..c03b24e41e38 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2201,7 +2201,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
 	eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
 
 	eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
-	if (USES_FULL_PPGTT(eb.i915))
+	if (USES_FULL_3LVL_PPGTT(eb.i915) || USES_FULL_4LVL_PPGTT(eb.i915))
 		eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
 	reloc_cache_init(&eb.reloc_cache, eb.i915);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4137af4bd8f5..263490d67c15 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -142,8 +142,8 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	if (!dev_priv->info.has_aliasing_ppgtt)
 		return 0;
 
-	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+	has_full_ppgtt = dev_priv->info.has_full_3lvl_ppgtt;
+	has_full_48bit_ppgtt = dev_priv->info.has_full_4lvl_ppgtt;
 
 	if (intel_vgpu_active(dev_priv)) {
 		/* GVT-g has no support for 32bit ppgtt */
@@ -1647,9 +1647,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
+	ppgtt->vm.total = i915->info.full_ppgtt_bits;
 
 	/*
 	 * From bdw, there is support for read-only pages in the PPGTT.
@@ -1788,7 +1786,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
 	enum intel_engine_id id;
 
 	for_each_engine(engine, dev_priv, id) {
-		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
+		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
 				 GEN8_GFX_PPGTT_48B : 0;
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
@@ -2958,7 +2956,9 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
+	if (USES_PPGTT(dev_priv) &&
+	    !USES_FULL_3LVL_PPGTT(dev_priv) &&
+	    !USES_FULL_4LVL_PPGTT(dev_priv)) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
@@ -3408,7 +3408,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 	ggtt->vm.cleanup = gen6_gmch_remove;
 	ggtt->vm.insert_page = gen8_ggtt_insert_page;
 	ggtt->vm.clear_range = nop_clear_range;
-	if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
+	if (intel_scanout_needs_vtd_wa(dev_priv) ||
+	    (!USES_FULL_3LVL_PPGTT(dev_priv) && !USES_FULL_4LVL_PPGTT(dev_priv)))
 		ggtt->vm.clear_range = gen8_ggtt_clear_range;
 
 	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..0454abc596b4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -298,7 +298,8 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_aliasing_ppgtt = 1, \
-	.has_full_ppgtt = 1, \
+	.has_full_3lvl_ppgtt = 1, \
+	.full_ppgtt_bits = 32, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -352,11 +353,12 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
 	.has_aliasing_ppgtt = 1,
-	.has_full_ppgtt = 1,
+	.has_full_3lvl_ppgtt = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
+	.full_ppgtt_bits = 32,
 	GEN_DEFAULT_PAGE_SIZES,
 	GEN_DEFAULT_PIPEOFFSETS,
 	CURSOR_OFFSETS
@@ -399,9 +401,10 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.has_full_4lvl_ppgtt = 1, \
 	.has_64bit_reloc = 1, \
-	.has_reset_engine = 1
+	.has_reset_engine = 1, \
+	.full_ppgtt_bits = 48
 
 #define BDW_PLATFORM \
 	GEN8_FEATURES, \
@@ -444,11 +447,12 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
 	.has_aliasing_ppgtt = 1,
-	.has_full_ppgtt = 1,
+	.has_full_3lvl_ppgtt = 1,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
+	.full_ppgtt_bits = 32,
 	GEN_DEFAULT_PAGE_SIZES,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -519,12 +523,12 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
 	.has_aliasing_ppgtt = 1, \
-	.has_full_ppgtt = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.has_full_4lvl_ppgtt = 1, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
 	.has_ipc = 1, \
+	.full_ppgtt_bits = 48, \
 	GEN9_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6eecd64734d5..df3263b97c7d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -87,8 +87,8 @@ enum intel_platform {
 	func(has_reset_engine); \
 	func(has_fbc); \
 	func(has_fpga_dbg); \
-	func(has_full_ppgtt); \
-	func(has_full_48bit_ppgtt); \
+	func(has_full_3lvl_ppgtt); \
+	func(has_full_4lvl_ppgtt); \
 	func(has_gmch_display); \
 	func(has_guc); \
 	func(has_guc_ct); \
@@ -182,6 +182,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* PPGTT bit size */
+	int full_ppgtt_bits;
 };
 
 struct intel_driver_caps {
-- 
2.14.4



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