[PATCH 3/9] bsw2

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem_fence_reg.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index d548ac05ccd7..6907157a2be2 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -109,7 +109,6 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
 
 		I915_WRITE(fence_reg_hi, upper_32_bits(val));
 		I915_WRITE(fence_reg_lo, lower_32_bits(val));
-		POSTING_READ(fence_reg_lo);
 	}
 }
 
@@ -149,7 +148,6 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *fence,
 		i915_reg_t reg = FENCE_REG(fence->id);
 
 		I915_WRITE(reg, val);
-		POSTING_READ(reg);
 	}
 }
 
@@ -181,14 +179,14 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *fence,
 		i915_reg_t reg = FENCE_REG(fence->id);
 
 		I915_WRITE(reg, val);
-		POSTING_READ(reg);
 	}
 }
 
 static void fence_write(struct drm_i915_fence_reg *fence,
 			struct i915_vma *vma)
 {
-	/* Previous access through the fence register is marshalled by
+	/*
+	 * Previous access through the fence register is marshalled by
 	 * the mb() inside the fault handlers (i915_gem_release_mmaps)
 	 * and explicitly managed for internal users.
 	 */
@@ -199,10 +197,7 @@ static void fence_write(struct drm_i915_fence_reg *fence,
 		i915_write_fence_reg(fence, vma);
 	else
 		i965_write_fence_reg(fence, vma);
-
-	/* Access through the fenced region afterwards is
-	 * ordered by the posting reads whilst writing the registers.
-	 */
+	mb();
 
 	fence->dirty = false;
 }
-- 
2.20.0.rc2