[PATCH 9/9] dbl-flush

[Chris Wilson]

---
 drivers/gpu/drm/i915/intel_lrc.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e6a86fa4502d..616d3d568bfb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1939,10 +1939,7 @@ static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
 static int gen8_emit_flush(struct i915_request *request, u32 mode)
 {
 	u32 cmd, *cs;
-
-	cs = intel_ring_begin(request, 4);
-	if (IS_ERR(cs))
-		return PTR_ERR(cs);
+	int repeat = 1;
 
 	cmd = MI_FLUSH_DW + 1;
 
@@ -1959,10 +1956,20 @@ static int gen8_emit_flush(struct i915_request *request, u32 mode)
 			cmd |= MI_INVALIDATE_BSD;
 	}
 
-	*cs++ = cmd;
-	*cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
-	*cs++ = 0; /* upper addr */
-	*cs++ = 0; /* value */
+	if (mode & EMIT_FLUSH)
+		repeat = 8;
+
+	cs = intel_ring_begin(request, 4 * repeat);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	for (i = 0; i < repeat; i++) {
+		*cs++ = cmd;
+		*cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
+		*cs++ = 0; /* upper addr */
+		*cs++ = 0; /* value */
+	}
+
 	intel_ring_advance(request, cs);
 
 	return 0;
-- 
2.20.0.rc2