✓ Fi.CI.BAT: success for series starting with [01/34] drm/i915/selftests: Flush old resets between engines
Patchwork
patchwork at emeril.freedesktop.org
Sun Feb 4 14:26:51 UTC 2018
== Series Details ==
Series: series starting with [01/34] drm/i915/selftests: Flush old resets between engines
URL : https://patchwork.freedesktop.org/series/37614/
State : success
== Summary ==
Series 37614v1 series starting with [01/34] drm/i915/selftests: Flush old resets between engines
https://patchwork.freedesktop.org/api/1.0/series/37614/revisions/1/mbox/
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test gem_ringfill:
Subgroup basic-default-hang:
dmesg-warn -> INCOMPLETE (fi-pnv-d510) fdo#101600
Test kms_frontbuffer_tracking:
Subgroup basic:
pass -> FAIL (fi-glk-1) fdo#103167
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:416s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:424s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:373s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:487s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:483s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:486s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:468s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:459s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:568s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:407s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:278s
fi-glk-1 total:288 pass:259 dwarn:0 dfail:0 fail:1 skip:28 time:509s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:389s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:398s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:413s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:455s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:414s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:456s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:495s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:451s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:500s
fi-pnv-d510 total:146 pass:113 dwarn:0 dfail:0 fail:0 skip:32
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:429s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:508s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:524s
fi-skl-6700k2 total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:486s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:490s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:416s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:428s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:392s
Blacklisted hosts:
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:467s
2e76a2952923eba64c4f9baf461613bc42ee997a drm-tip: 2018y-02m-02d-20h-33m-12s UTC integration manifest
0ffcec0ab1ee drm/i915: Reduce context HW ID lifetime
eea3746a5155 drm/i915: Move sandybride pcode access to intel_sideband.c
6a19cd78ec66 drm/i915: Merge sandybridge_pcode_(read|write)
95aad2f9efa3 drm/i915: Merge sbi read/write into a single accessor
5bb7d424d4f7 drm/i915: Separate sideband declarations to intel_sideband.h
79e64d9628a4 drm/i915: Replace pcu_lock with sb_lock
5409222907d7 Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
92047163f4f0 drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
f96b5da4b324 drm/i915: Lift sideband locking for vlv_punit_(read|write)
2b4e4ae715e1 drm/i915: Lift acquiring the vlv punit magic to a common sb-get
44d468cd3065 drm/i915: Disable preemption and sleeping while using the punit sideband
68fdb15771f1 drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list
af7725e303ce drm/i915: Only signal from interrupt when requested
28104a85b366 drm/i915: Move the irq_counter inside the spinlock
7d97448be76e drm/i915: Reduce spinlock hold time during notify_ring() interrupt
804513dd69ec drm/i915/breadcrumbs: Drop request reference for the signaler thread
93df3ec3cc97 drm/i915: Trim the retired request queue after submitting
7f6a1d34b01c drm/i915/selftests: Extend partial vma coverage to check parallel creation
d069c9de5030 drm/i915: Replace open-coded wait-for loop
dcce28b8c0a5 drm/i915/execlists: Remove the ring advancement under preemption
9d9740fbf3e3 drm/i915: Always update the no_fbc_reason when disabling
bfe60ea89c82 prune-fences
e3113d04cde7 dma-buf: Refactor reservation_object_add_shared_fence()
54c3128de8de drm/i915: Enable debugobjects for request validation
0dd6520dbfb6 drm/i915: Only allocate preempt context when required
8af64422b409 drm/i915: Move the scheduler feature bits into the purview of the engines
484567e5936c drm/i915/guc: Allow preempt-client to be NULL
319b0a212c23 drm/i915: Remove unbannable context spam from reset
c954238af74c drm/i915/execlists: Remove the startup spam
bce6f5bbdf06 drm/i915: Show the GPU state when declaring wedged
146164d6eeac drm/i915: Skip post-reset request emission if the engine is not idle
5f07dc924870 drm/i915/execlists: Move the reset bits to a more natural home
6b2c09b94ac5 drm/i915/selftests: Use a sacrificial context for hang testing
5ab1c38cc776 drm/i915/selftests: Flush old resets between engines
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_1754/issues.html
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