[PATCH 2/5] drm/i915: keep AUX powered while PSR is enabled

[Souza, Jose]

On Mon, 2018-02-12 at 23:26 -0800, Rodrigo Vivi wrote:
> On Tue, Feb 13, 2018 at 12:16:10AM +0000, José Roberto de Souza
> wrote:
> > Hardware can send AUX transactions by it self when PSR is enabled
> > and it
> > expects that AUX is kept powered up.
> > 
> > Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 8b456e4e1b47..225fde979e57 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -516,6 +516,12 @@ void intel_psr_enable(struct intel_dp
> > *intel_dp,
> >  		goto unlock;
> >  	}
> >  
> > +	/*
> > +	 * hardware can send AUX transactions by it self when PSR
> > is enabled,
> > +	 * and it expects that AUX is kept powered up.
> > +	 */
> > +	intel_display_power_get(dev_priv, intel_dp-
> > >aux_power_domain);
> > +
> 
> we actually kind of need the other way around... we need a way to
> block psr on aux transactions
> instead of making sure we have more power wells enabled when psr is
> enabled.
> 
> this approach here would kill some power savings

I agree that it will kill some of the power savings but when enabling
or disabling PSR hardware will do some aux transactions by it self, so
we need to guarantee that the power wells that have the aux ch is kept
powered otherwise hardware will not be able to do the aux ch
transactions.

> 
> >  	dev_priv->psr.psr2_support = crtc_state->has_psr2;
> >  	dev_priv->psr.busy_frontbuffer_bits = 0;
> >  
> > @@ -656,6 +662,8 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> >  	/* Disable PSR on Sink */
> >  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
> >  
> > +	intel_display_power_put(dev_priv, intel_dp-
> > >aux_power_domain);
> > +
> >  	dev_priv->psr.enabled = NULL;
> >  	mutex_unlock(&dev_priv->psr.lock);
> >  
> > -- 
> > 2.16.1
> > 
> 
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