[PATCH 01/10] drm/i915/guc: Move GuC interrupts related functions from i915_irq.c to intel_guc.c
Sagar Arun Kamble
sagar.a.kamble at intel.com
Tue Jan 9 07:38:54 UTC 2018
GuC interrupts handling is core GuC functionality. Better to keep it
with other core functions in intel_guc.c. Since they are used from
uC functions, GuC log and i915 irq handling we are keeping them grouped
in intel_guc.c instead of intel_uc.c. Also update the function parameter
from dev_priv to intel_guc struct while we are at it.
In order to separate GuC IRQ handling functions from i915_irq.c we need
to export the low level pm irq handlers. Export pm_iir, reset_pm_iir and
enable/disable_pm_irq functions.
v2-v3: Rebase.
v4: Squashed patches to change the parameter and move to guc.c. Using
readily available guc struct instead of referencing via dev_priv. (Michal)
s/intel_*_guc_interrupts/intel_guc_*_interrupts. (Chris)
Suggested-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> #v3
---
drivers/gpu/drm/i915/i915_irq.c | 78 +++-------------------------------
drivers/gpu/drm/i915/intel_drv.h | 7 ++--
drivers/gpu/drm/i915/intel_guc.c | 81 ++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_guc.h | 4 ++
drivers/gpu/drm/i915/intel_guc_log.c | 8 ++--
drivers/gpu/drm/i915/intel_uc.c | 8 ++--
6 files changed, 98 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c65..a1ae057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -203,7 +203,6 @@ static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
} while (0)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
/* For display hotplug interrupt */
static inline void
@@ -306,7 +305,7 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
ilk_update_gt_irq(dev_priv, mask, 0);
}
-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
+i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
{
return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}
@@ -369,7 +368,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
__gen6_mask_pm_irq(dev_priv, mask);
}
-static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
+void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
{
i915_reg_t reg = gen6_pm_iir(dev_priv);
@@ -380,7 +379,7 @@ static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
POSTING_READ(reg);
}
-static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
+void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
{
lockdep_assert_held(&dev_priv->irq_lock);
@@ -390,7 +389,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mas
/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
}
-static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
+void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
{
lockdep_assert_held(&dev_priv->irq_lock);
@@ -450,38 +449,6 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
gen6_reset_rps_interrupts(dev_priv);
}
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
-{
- spin_lock_irq(&dev_priv->irq_lock);
- gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
- spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
-{
- spin_lock_irq(&dev_priv->irq_lock);
- if (!dev_priv->guc.interrupts_enabled) {
- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
- dev_priv->pm_guc_events);
- dev_priv->guc.interrupts_enabled = true;
- gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
- }
- spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
-{
- spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->guc.interrupts_enabled = false;
-
- gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
-
- spin_unlock_irq(&dev_priv->irq_lock);
- synchronize_irq(dev_priv->drm.irq);
-
- gen9_reset_guc_interrupts(dev_priv);
-}
-
/**
* bdw_update_port_irq - update DE port interrupt
* @dev_priv: driver private
@@ -1480,7 +1447,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
gen6_rps_irq_handler(dev_priv, gt_iir[2]);
if (gt_iir[2] & dev_priv->pm_guc_events)
- gen9_guc_irq_handler(dev_priv, gt_iir[2]);
+ intel_guc_irq_handler(&dev_priv->guc, gt_iir[2]);
}
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
@@ -1757,41 +1724,6 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
}
}
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
-{
- if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
- /* Sample the log buffer flush related bits & clear them out now
- * itself from the message identity register to minimize the
- * probability of losing a flush interrupt, when there are back
- * to back flush interrupts.
- * There can be a new flush interrupt, for different log buffer
- * type (like for ISR), whilst Host is handling one (for DPC).
- * Since same bit is used in message register for ISR & DPC, it
- * could happen that GuC sets the bit for 2nd interrupt but Host
- * clears out the bit on handling the 1st interrupt.
- */
- u32 msg, flush;
-
- msg = I915_READ(SOFT_SCRATCH(15));
- flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
- INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
- if (flush) {
- /* Clear the message bits that are handled */
- I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
-
- /* Handle flush interrupt in bottom half */
- queue_work(dev_priv->guc.log.runtime.flush_wq,
- &dev_priv->guc.log.runtime.flush_work);
-
- dev_priv->guc.log.flush_interrupt_count++;
- } else {
- /* Not clearing of unhandled event bits won't result in
- * re-triggering of the interrupt.
- */
- }
- }
-}
-
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
{
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 731dc36..b60b877 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1313,8 +1313,12 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
/* i915_irq.c */
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
+i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv);
void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
+void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask);
+void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask);
+void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask);
void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
@@ -1341,9 +1345,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask);
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 pipe_mask);
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
/* intel_crt.c */
void intel_crt_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 50b4725..7278bde 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -257,7 +257,7 @@ void intel_guc_init_params(struct intel_guc *guc)
/* If GuC submission is enabled, set up additional parameters here */
if (USES_GUC_SUBMISSION(dev_priv)) {
u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
- u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
+ u32 pgs = guc_ggtt_offset(guc->stage_desc_pool);
u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
@@ -400,7 +400,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- gen9_disable_guc_interrupts(dev_priv);
+ intel_guc_disable_interrupts(guc);
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
/* any value greater than GUC_POWER_D0 */
@@ -446,7 +446,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
return 0;
if (i915_modparams.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
+ intel_guc_enable_interrupts(guc);
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
data[1] = GUC_POWER_D0;
@@ -507,3 +507,78 @@ u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
return wopcm_size;
}
+
+void intel_guc_reset_interrupts(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ spin_lock_irq(&dev_priv->irq_lock);
+ gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
+ spin_unlock_irq(&dev_priv->irq_lock);
+}
+
+void intel_guc_enable_interrupts(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (!guc->interrupts_enabled) {
+ WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
+ dev_priv->pm_guc_events);
+ guc->interrupts_enabled = true;
+ gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+ }
+ spin_unlock_irq(&dev_priv->irq_lock);
+}
+
+void intel_guc_disable_interrupts(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ spin_lock_irq(&dev_priv->irq_lock);
+ guc->interrupts_enabled = false;
+
+ gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
+
+ spin_unlock_irq(&dev_priv->irq_lock);
+ synchronize_irq(dev_priv->drm.irq);
+
+ intel_guc_reset_interrupts(guc);
+}
+
+void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
+ /* Sample the log buffer flush related bits & clear them out now
+ * itself from the message identity register to minimize the
+ * probability of losing a flush interrupt, when there are back
+ * to back flush interrupts.
+ * There can be a new flush interrupt, for different log buffer
+ * type (like for ISR), whilst Host is handling one (for DPC).
+ * Since same bit is used in message register for ISR & DPC, it
+ * could happen that GuC sets the bit for 2nd interrupt but Host
+ * clears out the bit on handling the 1st interrupt.
+ */
+ u32 msg, flush;
+
+ msg = I915_READ(SOFT_SCRATCH(15));
+ flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
+ INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
+ if (flush) {
+ /* Clear the message bits that are handled */
+ I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
+
+ /* Handle flush interrupt in bottom half */
+ queue_work(guc->log.runtime.flush_wq,
+ &guc->log.runtime.flush_work);
+
+ guc->log.flush_interrupt_count++;
+ } else {
+ /* Not clearing of unhandled event bits won't result in
+ * re-triggering of the interrupt.
+ */
+ }
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 52856a9..1df9222 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -131,5 +131,9 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
int intel_guc_resume(struct drm_i915_private *dev_priv);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
+void intel_guc_reset_interrupts(struct intel_guc *guc);
+void intel_guc_enable_interrupts(struct intel_guc *guc);
+void intel_guc_disable_interrupts(struct intel_guc *guc);
+void intel_guc_irq_handler(struct intel_guc *guc, u32 pm_iir);
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index eaedd63..84ae6f8 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -480,14 +480,12 @@ static void guc_log_capture_logs(struct intel_guc *guc)
static void guc_flush_logs(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
-
if (!USES_GUC_SUBMISSION(dev_priv) ||
(i915_modparams.guc_log_level < 0))
return;
/* First disable the interrupts, will be renabled afterwards */
- gen9_disable_guc_interrupts(dev_priv);
+ intel_guc_disable_interrupts(guc);
/* Before initiating the forceful flush, wait for any pending/ongoing
* flush to complete otherwise forceful flush may not actually happen.
@@ -605,7 +603,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
}
/* GuC logging is currently the only user of Guc2Host interrupts */
- gen9_enable_guc_interrupts(dev_priv);
+ intel_guc_enable_interrupts(guc);
} else {
/* Once logging is disabled, GuC won't generate logs & send an
* interrupt. But there could be some data in the log buffer
@@ -639,7 +637,7 @@ void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
- gen9_disable_guc_interrupts(dev_priv);
+ intel_guc_disable_interrupts(&dev_priv->guc);
guc_log_runtime_destroy(&dev_priv->guc);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 907deac..16ed558 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -271,7 +271,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
GEM_BUG_ON(!HAS_GUC(dev_priv));
guc_disable_communication(guc);
- gen9_reset_guc_interrupts(dev_priv);
+ intel_guc_reset_interrupts(guc);
/* init WOPCM */
I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
@@ -325,7 +325,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
if (USES_GUC_SUBMISSION(dev_priv)) {
if (i915_modparams.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
+ intel_guc_enable_interrupts(guc);
ret = intel_guc_submission_enable(guc);
if (ret)
@@ -345,7 +345,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
* We've failed to load the firmware :(
*/
err_interrupts:
- gen9_disable_guc_interrupts(dev_priv);
+ intel_guc_disable_interrupts(guc);
err_communication:
guc_disable_communication(guc);
err_log_capture:
@@ -379,5 +379,5 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
guc_disable_communication(guc);
if (USES_GUC_SUBMISSION(dev_priv))
- gen9_disable_guc_interrupts(dev_priv);
+ intel_guc_disable_interrupts(guc);
}
--
1.9.1
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