[PATCH 48/67] has-rps
Chris Wilson
chris at chris-wilson.co.uk
Thu Jan 11 12:37:23 UTC 2018
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_gt_pm.c | 20 ++++++++++++++++----
4 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9e7ad338d827..367dcb7a2bc8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2795,6 +2795,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
+#define HAS_RPS(dev_priv) ((dev_priv)->info.has_rps)
+
#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 36d48422b475..86aef877966a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -224,6 +224,7 @@ static const struct intel_device_info intel_ironlake_m_info __initconst = {
GEN5_FEATURES,
.platform = INTEL_IRONLAKE,
.is_mobile = 1, .has_fbc = 1,
+ .has_rps = true,
};
#define GEN6_FEATURES \
@@ -234,6 +235,7 @@ static const struct intel_device_info intel_ironlake_m_info __initconst = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+ .has_rps = true, \
.has_aliasing_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
@@ -277,6 +279,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst =
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
+ .has_rps = true, \
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -330,6 +333,7 @@ static const struct intel_device_info intel_valleyview_info __initconst = {
.has_psr = 1,
.has_runtime_pm = 1,
.has_rc6 = 1,
+ .has_rps = true,
.has_gmch_display = 1,
.has_hotplug = 1,
.has_aliasing_ppgtt = 1,
@@ -423,6 +427,7 @@ static const struct intel_device_info intel_cherryview_info __initconst = {
.has_runtime_pm = 1,
.has_resource_streamer = 1,
.has_rc6 = 1,
+ .has_rps = true,
.has_logical_ring_contexts = 1,
.has_gmch_display = 1,
.has_aliasing_ppgtt = 1,
@@ -496,6 +501,7 @@ static const struct intel_device_info intel_skylake_gt4_info __initconst = {
.has_csr = 1, \
.has_resource_streamer = 1, \
.has_rc6 = 1, \
+ .has_rps = true, \
.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 49cb27bd04c1..c67ec8cfc1f6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -100,6 +100,7 @@ enum intel_platform {
func(has_psr); \
func(has_rc6); \
func(has_rc6p); \
+ func(has_rps); \
func(has_resource_streamer); \
func(has_runtime_pm); \
func(has_snoop); \
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index 16499d913061..ab8098775958 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -432,6 +432,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ if (!HAS_RPS(dev_priv))
+ return;
+
mutex_lock(&rps->lock);
if (rps->enabled) {
u8 freq;
@@ -462,6 +465,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ if (!HAS_RPS(dev_priv))
+ return;
+
/* Flush our bottom-half so that it does not race with us
* setting the idle frequency and so that it is bounded by
* our rpm wakeref. And then disable the interrupts to stop any
@@ -489,6 +495,9 @@ void gen6_rps_boost(struct drm_i915_gem_request *rq,
unsigned long flags;
bool boost;
+ if (!HAS_RPS(rq->i915))
+ return;
+
/* This is intentionally racy! We peek at the state here, then
* validate inside the RPS worker.
*/
@@ -650,8 +659,10 @@ static bool sanitize_rc6(struct drm_i915_private *i915)
struct intel_device_info *info = mkwrite_device_info(i915);
/* Powersaving is controlled by the host when inside a VM */
- if (intel_vgpu_active(i915))
+ if (intel_vgpu_active(i915)) {
info->has_rc6 = 0;
+ info->has_rps = 0;
+ }
if (info->has_rc6 &&
IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
@@ -2192,7 +2203,7 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
valleyview_disable_rps(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rps(dev_priv);
- else if (IS_IRONLAKE_M(dev_priv))
+ else if (INTEL_GEN(dev_priv) >= 5)
ironlake_disable_drps(dev_priv);
dev_priv->gt_pm.rps.enabled = false;
@@ -2262,7 +2273,7 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
gen8_enable_rps(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 6) {
gen6_enable_rps(dev_priv);
- } else if (IS_IRONLAKE_M(dev_priv)) {
+ } else if (INTEL_GEN(dev_priv) >= 5) {
ironlake_enable_drps(dev_priv);
intel_init_emon(dev_priv);
}
@@ -2286,7 +2297,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
if (HAS_RC6(dev_priv))
intel_enable_rc6(dev_priv);
- intel_enable_rps(dev_priv);
+ if (HAS_RPS(dev_priv))
+ intel_enable_rps(dev_priv);
if (HAS_LLC(dev_priv))
intel_enable_llc_pstate(dev_priv);
--
2.15.1
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