[PATCH 59/64] drm/i915: Make the RPS interface gen agnostic
Chris Wilson
chris at chris-wilson.co.uk
Fri Jan 19 00:22:52 UTC 2018
This is a preparation patch to change the interface over from gen6+ to
any so that we can extend the RPS infrastructure to support earlier
generations in subsequent patches.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 10 +++-------
drivers/gpu/drm/i915/i915_gem_request.c | 3 +--
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_gt_pm.c | 25 ++++++++++++++++---------
drivers/gpu/drm/i915/intel_gt_pm.h | 8 ++++----
5 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a28c06018532..bed9adf0cd81 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -388,10 +388,8 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
* forcing the clocks too high for the whole system, we only allow
* each client to waitboost once in a busy period.
*/
- if (rps_client && !i915_gem_request_started(rq)) {
- if (INTEL_GEN(rq->i915) >= 6)
- gen6_rps_boost(rq, rps_client);
- }
+ if (rps_client && !i915_gem_request_started(rq))
+ intel_rps_boost(rq, rps_client);
timeout = i915_wait_request(rq, flags, timeout);
@@ -4836,15 +4834,13 @@ i915_gem_idle_work_handler(struct work_struct *work)
i915_pmu_gt_parked(dev_priv);
- if (INTEL_GEN(dev_priv) >= 6)
- gen6_rps_idle(dev_priv);
+ intel_rps_idle(dev_priv);
GEM_BUG_ON(!dev_priv->gt.awake);
dev_priv->gt.awake = false;
rearm_hangcheck = false;
intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
-
intel_runtime_pm_put(dev_priv);
out_unlock:
mutex_unlock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 24e7db216e37..cb4222306e3c 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -277,8 +277,7 @@ static void mark_busy(struct drm_i915_private *i915)
i915->gt.awake = true;
i915_update_gfx_val(i915);
- if (INTEL_GEN(i915) >= 6)
- gen6_rps_busy(i915);
+ intel_rps_busy(i915);
i915_pmu_gt_unparked(i915);
intel_engines_unpark(i915);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c936c0903a5f..657568ca1d71 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12526,7 +12526,7 @@ static int do_rps_boost(struct wait_queue_entry *_wait,
* vblank without our intervention, so leave RPS alone.
*/
if (!i915_gem_request_started(rq))
- gen6_rps_boost(rq, NULL);
+ intel_rps_boost(rq, NULL);
i915_gem_request_put(rq);
drm_crtc_vblank_put(wait->crtc);
@@ -12544,7 +12544,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
if (!dma_fence_is_i915(fence))
return;
- if (INTEL_GEN(to_i915(crtc->dev)) < 6)
+ if (!HAS_RPS(to_i915(crtc->dev)))
return;
if (drm_crtc_vblank_get(crtc))
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index bdad521df720..d83300735e12 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -51,7 +51,6 @@
* require higher latency to switch to and wake up.
*/
-
/*
* Lock protecting IPS related data structures
*/
@@ -395,6 +394,7 @@ static int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
struct intel_rps *rps = &dev_priv->gt_pm.rps;
lockdep_assert_held(&rps->lock);
+ GEM_BUG_ON(!HAS_RPS(dev_priv));
GEM_BUG_ON(val > rps->max_freq);
GEM_BUG_ON(val < rps->min_freq);
@@ -533,7 +533,7 @@ static void intel_rps_work(struct work_struct *work)
}
}
-void gen6_rps_busy(struct drm_i915_private *dev_priv)
+void intel_rps_busy(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
u8 freq;
@@ -555,13 +555,16 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("Failed to set busy frequency\n");
rps->last_adj = 0;
+
mutex_unlock(&rps->lock);
- memset(&rps->ei, 0, sizeof(rps->ei));
- gen6_enable_rps_interrupts(dev_priv);
+ if (INTEL_GEN(dev_priv) >= 6) {
+ memset(&rps->ei, 0, sizeof(rps->ei));
+ gen6_enable_rps_interrupts(dev_priv);
+ }
}
-void gen6_rps_idle(struct drm_i915_private *dev_priv)
+void intel_rps_idle(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -574,7 +577,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
* our rpm wakeref. And then disable the interrupts to stop any
* futher RPS reclocking whilst we are asleep.
*/
- gen6_disable_rps_interrupts(dev_priv);
+ if (INTEL_GEN(dev_priv) >= 6)
+ gen6_disable_rps_interrupts(dev_priv);
mutex_lock(&rps->lock);
@@ -599,13 +603,16 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
}
- I915_WRITE(GEN6_PMINTRMSK,
- gen6_sanitize_rps_pm_mask(dev_priv, ~0));
+ if (INTEL_GEN(dev_priv) >= 6) {
+ I915_WRITE(GEN6_PMINTRMSK,
+ gen6_sanitize_rps_pm_mask(dev_priv, ~0));
+ }
+ rps->last_adj = 0;
mutex_unlock(&rps->lock);
}
-void gen6_rps_boost(struct drm_i915_gem_request *rq,
+void intel_rps_boost(struct drm_i915_gem_request *rq,
struct intel_rps_client *rps_client)
{
struct intel_rps *rps = &rq->i915->gt_pm.rps;
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
index d7715995cb8e..fd2dbe381f32 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -38,10 +38,10 @@ void intel_gt_disable_rps(struct drm_i915_private *dev_priv);
void intel_gt_enable_rc6(struct drm_i915_private *dev_priv);
void intel_gt_disable_rc6(struct drm_i915_private *dev_priv);
-void gen6_rps_busy(struct drm_i915_private *dev_priv);
-void gen6_rps_idle(struct drm_i915_private *dev_priv);
-void gen6_rps_boost(struct drm_i915_gem_request *rq,
- struct intel_rps_client *rps);
+void intel_rps_busy(struct drm_i915_private *dev_priv);
+void intel_rps_idle(struct drm_i915_private *dev_priv);
+void intel_rps_boost(struct drm_i915_gem_request *rq,
+ struct intel_rps_client *rps);
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
--
2.15.1
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