[PATCH 60/66] drm/i915: Rename rps min/max frequencies
Chris Wilson
chris at chris-wilson.co.uk
Sat Jan 20 19:44:22 UTC 2018
In preparation for more layers of limits, rename the existing limits to
hw and user.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 35 ++++----
drivers/gpu/drm/i915/i915_drv.h | 21 +++--
drivers/gpu/drm/i915/i915_pmu.c | 4 +-
drivers/gpu/drm/i915/i915_sysfs.c | 23 ++---
drivers/gpu/drm/i915/intel_gt_pm.c | 170 ++++++++++++++++++------------------
5 files changed, 128 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fda03c2c779f..130b3dedffe6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1045,13 +1045,13 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
seq_printf(m, "current GPU freq: %d MHz\n",
- intel_gpu_freq(dev_priv, rps->cur_freq));
+ intel_gpu_freq(dev_priv, rps->freq));
seq_printf(m, "max GPU freq: %d MHz\n",
- intel_gpu_freq(dev_priv, rps->max_freq));
+ intel_gpu_freq(dev_priv, rps->max_freq_hw));
seq_printf(m, "min GPU freq: %d MHz\n",
- intel_gpu_freq(dev_priv, rps->min_freq));
+ intel_gpu_freq(dev_priv, rps->min_freq_hw));
seq_printf(m, "idle GPU freq: %d MHz\n",
intel_gpu_freq(dev_priv, rps->idle_freq));
@@ -1183,19 +1183,19 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
intel_gpu_freq(dev_priv, max_freq));
seq_printf(m, "Max overclocked frequency: %dMHz\n",
- intel_gpu_freq(dev_priv, rps->max_freq));
+ intel_gpu_freq(dev_priv, rps->max_freq_hw));
seq_printf(m, "Current freq: %d MHz\n",
- intel_gpu_freq(dev_priv, rps->cur_freq));
+ intel_gpu_freq(dev_priv, rps->freq));
seq_printf(m, "Actual freq: %d MHz\n", cagf);
seq_printf(m, "Idle freq: %d MHz\n",
intel_gpu_freq(dev_priv, rps->idle_freq));
seq_printf(m, "Min freq: %d MHz\n",
- intel_gpu_freq(dev_priv, rps->min_freq));
+ intel_gpu_freq(dev_priv, rps->min_freq_hw));
seq_printf(m, "Boost freq: %d MHz\n",
intel_gpu_freq(dev_priv, rps->boost_freq));
seq_printf(m, "Max freq: %d MHz\n",
- intel_gpu_freq(dev_priv, rps->max_freq));
+ intel_gpu_freq(dev_priv, rps->max_freq_hw));
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv, rps->efficient_freq));
@@ -1758,9 +1758,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
if (!HAS_LLC(dev_priv))
return -ENODEV;
- min_gpu_freq = rps->min_freq;
- max_gpu_freq = rps->max_freq;
-
+ min_gpu_freq = rps->min_freq_hw;
+ max_gpu_freq = rps->max_freq_hw;
if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
/* Convert GT frequency to 50 HZ units */
min_gpu_freq /= GEN9_FREQ_SCALER;
@@ -2155,13 +2154,15 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
seq_printf(m, "Boosts outstanding? %d\n",
atomic_read(&rps->num_waiters));
- seq_printf(m, "Frequency requested %d\n",
- intel_gpu_freq(dev_priv, rps->cur_freq));
- seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
- intel_gpu_freq(dev_priv, rps->min_freq),
- intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
- intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
- intel_gpu_freq(dev_priv, rps->max_freq));
+ seq_printf(m, "Frequency requested %d [%d, %d]\n",
+ intel_gpu_freq(dev_priv, rps->freq),
+ intel_gpu_freq(dev_priv, rps->min),
+ intel_gpu_freq(dev_priv, rps->max));
+ seq_printf(m, " min hard:%d, user:%d; max user:%d, hard:%d\n",
+ intel_gpu_freq(dev_priv, rps->min_freq_hw),
+ intel_gpu_freq(dev_priv, rps->min_freq_user),
+ intel_gpu_freq(dev_priv, rps->max_freq_user),
+ intel_gpu_freq(dev_priv, rps->max_freq_hw));
seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
intel_gpu_freq(dev_priv, rps->idle_freq),
intel_gpu_freq(dev_priv, rps->efficient_freq),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a571f2bb0341..bd1158a58983 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -900,7 +900,8 @@ struct intel_rps {
/* PM interrupt bits that should never be masked */
u32 pm_intrmsk_mbz;
- /* Frequencies are stored in potentially platform dependent multiples.
+ /*
+ * Frequencies are stored in potentially platform dependent multiples.
* In other words, *_freq needs to be multiplied by X to be interesting.
* Soft limits are those which are used for the dynamic reclocking done
* by the driver (raise frequencies under heavy loads, and lower for
@@ -910,16 +911,22 @@ struct intel_rps {
* default, and is considered to be above the hard limit if it's
* possible at all.
*/
- u8 cur_freq; /* Current frequency (cached, may not == HW) */
- u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
- u8 max_freq_softlimit; /* Max frequency permitted by the driver */
- u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
- u8 min_freq; /* AKA RPn. Minimum frequency */
- u8 boost_freq; /* Frequency to request when wait boosting */
+ u8 freq; /* Current frequency (cached, may not == HW) */
+ u8 min;
+ u8 max;
+
+ u8 min_freq_hw; /* AKA RPn. Minimum frequency */
+ u8 max_freq_hw; /* Maximum frequency, RP0 if not overclocking */
+ u8 min_freq_user; /* Minimum frequency permitted by the driver */
+ u8 max_freq_user; /* Max frequency permitted by the driver */
+
u8 idle_freq; /* Frequency to request when we are idle */
u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
+ u8 boost_freq; /* Frequency to request when wait boosting */
+
u8 rp1_freq; /* "less than" RP0 power/freqency */
u8 rp0_freq; /* Non-overclocked max frequency. */
+
u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
u8 up_threshold; /* Current %busy required to uplock */
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index f88b02c4d712..59c2ba070bae 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -235,7 +235,7 @@ static void frequency_sample(struct drm_i915_private *dev_priv)
config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
u32 val;
- val = dev_priv->gt_pm.rps.cur_freq;
+ val = dev_priv->gt_pm.rps.freq;
if (dev_priv->gt.awake &&
intel_runtime_pm_get_if_in_use(dev_priv)) {
val = intel_get_cagf(dev_priv,
@@ -251,7 +251,7 @@ static void frequency_sample(struct drm_i915_private *dev_priv)
config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
update_sample(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_REQ], 1,
intel_gpu_freq(dev_priv,
- dev_priv->gt_pm.rps.cur_freq));
+ dev_priv->gt_pm.rps.freq));
}
}
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 0db317b68296..7ac6d7b4a722 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -286,8 +286,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
return snprintf(buf, PAGE_SIZE, "%d\n",
- intel_gpu_freq(dev_priv,
- dev_priv->gt_pm.rps.cur_freq));
+ intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.freq));
}
static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
@@ -315,7 +314,7 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
/* Validate against (static) hardware limits */
val = intel_freq_opcode(dev_priv, val);
- if (val < rps->min_freq || val > rps->max_freq)
+ if (val < rps->min_freq_hw || val > rps->max_freq_hw)
return -EINVAL;
mutex_lock(&rps->lock);
@@ -346,7 +345,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
return snprintf(buf, PAGE_SIZE, "%d\n",
intel_gpu_freq(dev_priv,
- dev_priv->gt_pm.rps.max_freq_softlimit));
+ dev_priv->gt_pm.rps.max_freq_user));
}
static ssize_t gt_max_freq_mhz_store(struct device *kdev,
@@ -365,9 +364,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
val = intel_freq_opcode(dev_priv, val);
mutex_lock(&rps->lock);
- if (val < rps->min_freq ||
- val > rps->max_freq ||
- val < rps->min_freq_softlimit) {
+ if (val < rps->min_freq_user || val > rps->max_freq_hw) {
ret = -EINVAL;
goto unlock;
}
@@ -376,7 +373,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
DRM_DEBUG("User requested overclocking to %d\n",
intel_gpu_freq(dev_priv, val));
- rps->max_freq_softlimit = val;
+ rps->max_freq_user = val;
schedule_work(&rps->work);
unlock:
@@ -392,7 +389,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
return snprintf(buf, PAGE_SIZE, "%d\n",
intel_gpu_freq(dev_priv,
- dev_priv->gt_pm.rps.min_freq_softlimit));
+ dev_priv->gt_pm.rps.min_freq_user));
}
static ssize_t gt_min_freq_mhz_store(struct device *kdev,
@@ -411,14 +408,12 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
val = intel_freq_opcode(dev_priv, val);
mutex_lock(&rps->lock);
- if (val < rps->min_freq ||
- val > rps->max_freq ||
- val > rps->max_freq_softlimit) {
+ if (val < rps->min_freq_hw || val > rps->max_freq_user) {
ret = -EINVAL;
goto unlock;
}
- rps->min_freq_softlimit = val;
+ rps->min_freq_user = val;
schedule_work(&rps->work);
unlock:
@@ -453,7 +448,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
else if (attr == &dev_attr_gt_RP1_freq_mhz)
val = intel_gpu_freq(dev_priv, rps->rp1_freq);
else if (attr == &dev_attr_gt_RPn_freq_mhz)
- val = intel_gpu_freq(dev_priv, rps->min_freq);
+ val = intel_gpu_freq(dev_priv, rps->min_freq_hw);
else
BUG();
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index 4ade1fa1d767..24fe53e7dc49 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -190,13 +190,13 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
* frequency, if the down threshold expires in that window we will not
* receive a down interrupt. */
if (INTEL_GEN(dev_priv) >= 9) {
- limits = (rps->max_freq_softlimit) << 23;
- if (val <= rps->min_freq_softlimit)
- limits |= (rps->min_freq_softlimit) << 14;
+ limits = rps->max << 23;
+ if (val <= rps->min)
+ limits |= rps->min << 14;
} else {
- limits = rps->max_freq_softlimit << 24;
- if (val <= rps->min_freq_softlimit)
- limits |= rps->min_freq_softlimit << 16;
+ limits = rps->max << 24;
+ if (val <= rps->min)
+ limits |= rps->min << 16;
}
return limits;
@@ -212,30 +212,27 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
new_power = rps->power;
switch (rps->power) {
case LOW_POWER:
- if (val > rps->efficient_freq + 1 &&
- val > rps->cur_freq)
+ if (val > rps->efficient_freq + 1 && val > rps->freq)
new_power = BETWEEN;
break;
case BETWEEN:
- if (val <= rps->efficient_freq &&
- val < rps->cur_freq)
+ if (val <= rps->efficient_freq && val < rps->freq)
new_power = LOW_POWER;
- else if (val >= rps->rp0_freq &&
- val > rps->cur_freq)
+ else if (val >= rps->rp0_freq && val > rps->freq)
new_power = HIGH_POWER;
break;
case HIGH_POWER:
if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
- val < rps->cur_freq)
+ val < rps->freq)
new_power = BETWEEN;
break;
}
/* Max/min bins are special */
- if (val <= rps->min_freq_softlimit)
+ if (val <= rps->min)
new_power = LOW_POWER;
- if (val >= rps->max_freq_softlimit)
+ if (val >= rps->max)
new_power = HIGH_POWER;
if (new_power == rps->power)
return;
@@ -318,9 +315,9 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
u32 mask = 0;
/* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
- if (val > rps->min_freq_softlimit)
+ if (val > rps->min)
mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
- if (val < rps->max_freq_softlimit)
+ if (val < rps->max)
mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
mask &= dev_priv->pm_rps_events;
@@ -333,7 +330,7 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
* update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
{
- if (val != dev_priv->gt_pm.rps.cur_freq) {
+ if (val != dev_priv->gt_pm.rps.freq) {
if (INTEL_GEN(dev_priv) >= 9)
I915_WRITE(GEN6_RPNSWREQ, GEN9_FREQUENCY(val));
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
@@ -365,7 +362,7 @@ static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
"Odd GPU freq value\n"))
val &= ~1;
- if (val != dev_priv->gt_pm.rps.cur_freq) {
+ if (val != dev_priv->gt_pm.rps.freq) {
vlv_punit_get(dev_priv);
err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
vlv_punit_put(dev_priv);
@@ -389,14 +386,15 @@ static int __intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
return 0;
}
-static int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
+static int intel_set_rps(struct drm_i915_private *dev_priv, int freq)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ u8 val = clamp_t(int, freq, rps->min, rps->max);
lockdep_assert_held(&rps->lock);
GEM_BUG_ON(!HAS_RPS(dev_priv));
- GEM_BUG_ON(val > rps->max_freq);
- GEM_BUG_ON(val < rps->min_freq);
+ GEM_BUG_ON(val > rps->max_freq_hw);
+ GEM_BUG_ON(val < rps->min_freq_hw);
if (dev_priv->gt.awake) {
int err = __intel_set_rps(dev_priv, val);
@@ -404,9 +402,9 @@ static int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
return err;
}
- if (val != rps->cur_freq) {
+ if (val != rps->freq) {
trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
- rps->cur_freq = val;
+ rps->freq = val;
}
return 0;
@@ -476,17 +474,17 @@ static void intel_rps_work(struct work_struct *work)
mutex_lock(&rps->lock);
- min = rps->min_freq_softlimit;
- max = rps->max_freq_softlimit;
+ min = rps->min_freq_user;
+ max = rps->max_freq_user;
if (client_boost && max < rps->boost_freq)
max = rps->boost_freq;
- GEM_BUG_ON(min < rps->min_freq);
- GEM_BUG_ON(max > rps->max_freq);
+ GEM_BUG_ON(min < rps->min_freq_hw);
+ GEM_BUG_ON(max > rps->max_freq_hw);
GEM_BUG_ON(max < min);
adj = rps->last_adj;
- freq = rps->cur_freq;
+ freq = rps->freq;
if (client_boost && freq < rps->boost_freq) {
freq = rps->boost_freq;
adj = 0;
@@ -522,7 +520,10 @@ static void intel_rps_work(struct work_struct *work)
if (pm_iir)
rps->last_adj = adj;
- if (intel_set_rps(i915, clamp_t(int, freq + adj, min, max))) {
+ rps->min = min;
+ rps->max = max;
+
+ if (intel_set_rps(i915, freq + adj)) {
DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
rps->last_adj = 0;
}
@@ -540,7 +541,6 @@ static void intel_rps_work(struct work_struct *work)
void intel_rps_busy(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
- u8 freq;
if (!HAS_RPS(dev_priv))
return;
@@ -551,11 +551,7 @@ void intel_rps_busy(struct drm_i915_private *dev_priv)
* Use the user's desired frequency as a guide, but for better
* performance, jump directly to RPe as our starting frequency.
*/
- freq = max(rps->cur_freq, rps->efficient_freq);
- if (intel_set_rps(dev_priv,
- clamp(freq,
- rps->min_freq_softlimit,
- rps->max_freq_softlimit)))
+ if (intel_set_rps(dev_priv, max(rps->freq, rps->efficient_freq)))
DRM_DEBUG_DRIVER("Failed to set busy frequency\n");
rps->last_adj = 0;
@@ -586,7 +582,7 @@ void intel_rps_idle(struct drm_i915_private *dev_priv)
mutex_lock(&rps->lock);
- if (rps->cur_freq > rps->idle_freq) {
+ if (rps->freq > rps->idle_freq) {
/*
* The punit delays the write of the frequency and voltage
* until it determines the GPU is awake. During normal usage we
@@ -602,9 +598,11 @@ void intel_rps_idle(struct drm_i915_private *dev_priv)
* takes a lot less power than the render powerwell.
*/
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
- if (intel_set_rps(dev_priv, rps->idle_freq))
+ if (__intel_set_rps(dev_priv, rps->idle_freq))
DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
+
+ rps->freq = rps->idle_freq;
}
if (INTEL_GEN(dev_priv) >= 6) {
@@ -640,7 +638,7 @@ void intel_rps_boost(struct drm_i915_gem_request *rq,
if (!boost)
return;
- if (READ_ONCE(rps->cur_freq) < rps->boost_freq)
+ if (READ_ONCE(rps->freq) < rps->boost_freq)
schedule_work(&rps->work);
atomic_inc(rps_client ? &rps_client->boosts : &rps->boosts);
@@ -788,20 +786,20 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
/* All of these values are in units of 50MHz */
- /* static values from HW: RP0 > RP1 > RPn (min_freq) */
+ /* static values from HW: RP0 > RP1 > RPn (min_freq_hw) */
if (IS_GEN9_LP(dev_priv)) {
u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
- rps->min_freq = (rp_state_cap >> 0) & 0xff;
+ rps->min_freq_hw = (rp_state_cap >> 0) & 0xff;
} else {
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
rps->rp0_freq = (rp_state_cap >> 0) & 0xff;
rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
- rps->min_freq = (rp_state_cap >> 16) & 0xff;
+ rps->min_freq_hw = (rp_state_cap >> 16) & 0xff;
}
/* hw_max = RP0 until we check for overclocking */
- rps->max_freq = rps->rp0_freq;
+ rps->max_freq_hw = rps->rp0_freq;
rps->efficient_freq = rps->rp1_freq;
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
@@ -814,8 +812,8 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
rps->efficient_freq =
clamp_t(u8,
((ddcc_status >> 8) & 0xff),
- rps->min_freq,
- rps->max_freq);
+ rps->min_freq_hw,
+ rps->max_freq_hw);
}
if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
@@ -824,8 +822,8 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
*/
rps->rp0_freq *= GEN9_FREQ_SCALER;
rps->rp1_freq *= GEN9_FREQ_SCALER;
- rps->min_freq *= GEN9_FREQ_SCALER;
- rps->max_freq *= GEN9_FREQ_SCALER;
+ rps->min_freq_hw *= GEN9_FREQ_SCALER;
+ rps->max_freq_hw *= GEN9_FREQ_SCALER;
rps->efficient_freq *= GEN9_FREQ_SCALER;
}
}
@@ -974,8 +972,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
/* Docs recommend 900MHz, and 300 MHz respectively */
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
- rps->max_freq_softlimit << 24 |
- rps->min_freq_softlimit << 16);
+ rps->max_freq_hw << 24 |
+ rps->min_freq_hw << 16);
I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
@@ -1112,13 +1110,12 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
/* convert DDR frequency from units of 266.6MHz to bandwidth */
min_ring_freq = mult_frac(min_ring_freq, 8, 3);
+ min_gpu_freq = rps->min_freq_hw;
+ max_gpu_freq = rps->max_freq_hw;
if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
/* Convert GT frequency to 50 HZ units */
- min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER;
- max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER;
- } else {
- min_gpu_freq = rps->min_freq;
- max_gpu_freq = rps->max_freq;
+ min_gpu_freq /= GEN9_FREQ_SCALER;
+ max_gpu_freq /= GEN9_FREQ_SCALER;
}
/*
@@ -1409,11 +1406,11 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
}
DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
- rps->max_freq = valleyview_rps_max_freq(dev_priv);
- rps->rp0_freq = rps->max_freq;
+ rps->max_freq_hw = valleyview_rps_max_freq(dev_priv);
+ rps->rp0_freq = rps->max_freq_hw;
DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(dev_priv, rps->max_freq),
- rps->max_freq);
+ intel_gpu_freq(dev_priv, rps->max_freq_hw),
+ rps->max_freq_hw);
rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv);
DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
@@ -1425,10 +1422,10 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
intel_gpu_freq(dev_priv, rps->rp1_freq),
rps->rp1_freq);
- rps->min_freq = valleyview_rps_min_freq(dev_priv);
+ rps->min_freq_hw = valleyview_rps_min_freq(dev_priv);
DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(dev_priv, rps->min_freq),
- rps->min_freq);
+ intel_gpu_freq(dev_priv, rps->min_freq_hw),
+ rps->min_freq_hw);
vlv_iosf_sb_put(dev_priv,
BIT(VLV_IOSF_SB_PUNIT) |
@@ -1462,11 +1459,11 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
}
DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
- rps->max_freq = cherryview_rps_max_freq(dev_priv);
- rps->rp0_freq = rps->max_freq;
+ rps->max_freq_hw = cherryview_rps_max_freq(dev_priv);
+ rps->rp0_freq = rps->max_freq_hw;
DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(dev_priv, rps->max_freq),
- rps->max_freq);
+ intel_gpu_freq(dev_priv, rps->max_freq_hw),
+ rps->max_freq_hw);
rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv);
DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
@@ -1478,18 +1475,18 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
intel_gpu_freq(dev_priv, rps->rp1_freq),
rps->rp1_freq);
- rps->min_freq = cherryview_rps_min_freq(dev_priv);
+ rps->min_freq_hw = cherryview_rps_min_freq(dev_priv);
DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(dev_priv, rps->min_freq),
- rps->min_freq);
+ intel_gpu_freq(dev_priv, rps->min_freq_hw),
+ rps->min_freq_hw);
vlv_iosf_sb_put(dev_priv,
BIT(VLV_IOSF_SB_PUNIT) |
BIT(VLV_IOSF_SB_NC) |
BIT(VLV_IOSF_SB_CCK));
- WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
- rps->min_freq) & 1,
+ WARN_ONCE((rps->max_freq_hw | rps->efficient_freq | rps->rp1_freq |
+ rps->min_freq_hw) & 1,
"Odd GPU freq values\n");
}
@@ -1869,7 +1866,7 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
lockdep_assert_held(&mchdev_lock);
- pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));
+ pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.freq));
pxvid = (pxvid >> 24) & 0x7f;
ext_v = pvid_to_extvid(dev_priv, pxvid);
@@ -2190,14 +2187,13 @@ void intel_gt_pm_init(struct drm_i915_private *dev_priv)
gen6_init_rps_frequencies(dev_priv);
/* Derive initial user preferences/limits from the hardware limits */
- rps->idle_freq = rps->min_freq;
- rps->cur_freq = rps->idle_freq;
+ rps->idle_freq = rps->min_freq_hw;
- rps->max_freq_softlimit = rps->max_freq;
- rps->min_freq_softlimit = rps->min_freq;
+ rps->max_freq_user = rps->max_freq_hw;
+ rps->min_freq_user = rps->min_freq_hw;
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- rps->min_freq_softlimit =
+ rps->min_freq_user =
max_t(int,
rps->efficient_freq,
intel_freq_opcode(dev_priv, 450));
@@ -2210,14 +2206,18 @@ void intel_gt_pm_init(struct drm_i915_private *dev_priv)
sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, ¶ms);
if (params & BIT(31)) { /* OC supported */
DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
- (rps->max_freq & 0xff) * 50,
+ (rps->max_freq_hw & 0xff) * 50,
(params & 0xff) * 50);
- rps->max_freq = params & 0xff;
+ rps->max_freq_hw = params & 0xff;
}
}
/* Finally allow us to boost to max by default */
- rps->boost_freq = rps->max_freq;
+ rps->boost_freq = rps->max_freq_hw;
+
+ rps->freq = rps->idle_freq;
+ rps->min = rps->min_freq_hw;
+ rps->max = rps->max_freq_hw;
if (INTEL_GEN(dev_priv) >= 6)
gen6_update_ring_freq(dev_priv);
@@ -2262,18 +2262,18 @@ static void __enable_rps(struct drm_i915_private *dev_priv)
intel_init_emon(dev_priv);
}
- WARN_ON(rps->max_freq < rps->min_freq);
- WARN_ON(rps->idle_freq > rps->max_freq);
+ WARN_ON(rps->max_freq_hw < rps->min_freq_hw);
+ WARN_ON(rps->idle_freq > rps->max_freq_hw);
- WARN_ON(rps->efficient_freq < rps->min_freq);
- WARN_ON(rps->efficient_freq > rps->max_freq);
+ WARN_ON(rps->efficient_freq < rps->min_freq_hw);
+ WARN_ON(rps->efficient_freq > rps->max_freq_hw);
/* Force a reset */
- rps->cur_freq = rps->max_freq;
+ rps->freq = rps->max_freq_hw;
rps->power = -1;
__intel_set_rps(dev_priv, rps->idle_freq);
- rps->cur_freq = rps->idle_freq;
+ rps->freq = rps->idle_freq;
}
void intel_gt_enable_rc6(struct drm_i915_private *dev_priv)
--
2.15.1
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