[PATCH 3/3] 3

Chris Wilson chris at chris-wilson.co.uk
Wed Jan 31 23:15:33 UTC 2018


---
 drivers/gpu/drm/i915/intel_lrc.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 40dbeaee9dfa..9339809daccb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1462,6 +1462,8 @@ static void enable_execlists(struct intel_engine_cs *engine)
 	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
 		   engine->status_page.ggtt_offset);
 	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
+
+	engine->execlists.csb_head = -1;
 }
 
 static int gen8_init_common_ring(struct intel_engine_cs *engine)
@@ -1479,11 +1481,6 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
 	enable_execlists(engine);
 	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
 
-	GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
-
-	execlists->csb_head = -1;
-	execlists->active = 0;
-
 	/* After a GPU reset, we may have requests to replay */
 	if (execlists->first)
 		tasklet_schedule(&execlists->tasklet);
@@ -1528,6 +1525,8 @@ static void reset_irq(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
+	GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
+
 	/*
 	 * Clear any pending interrupt state.
 	 *
@@ -1540,6 +1539,8 @@ static void reset_irq(struct intel_engine_cs *engine)
 	I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
 		   GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
 	clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+	
+	engine->execlists.active = 0;
 }
 
 static void reset_common_ring(struct intel_engine_cs *engine,
-- 
2.15.1



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