[PATCH 3/3] tk3
Chris Wilson
chris at chris-wilson.co.uk
Sun Jul 8 18:34:54 UTC 2018
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 25 +++++++-----------------
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 978120f88de5..15e373c8ea8b 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -170,13 +170,6 @@ static void irq_enable(struct intel_engine_cs *engine)
*/
GEM_BUG_ON(!intel_irqs_enabled(engine->i915));
- /*
- * Enabling the IRQ may miss the generation of the interrupt, but
- * we still need to force the barrier before reading the seqno,
- * just in case.
- */
- set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
-
/* Caller disables interrupts */
if (engine->irq_enable) {
spin_lock(&engine->i915->irq_lock);
@@ -472,14 +465,6 @@ static bool __intel_engine_add_wait(struct intel_engine_cs *engine,
*/
armed = __intel_breadcrumbs_enable_irq(b);
spin_unlock(&b->irq_lock);
-
- /*
- * On taking over the principle irq waiter slot, we
- * have to be careful in case we miss the interrupt for
- * our breadcrumb and so require a full coherency barrier
- * just in case.
- */
- set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
}
if (completed) {
@@ -522,9 +507,13 @@ bool intel_engine_add_wait(struct intel_engine_cs *engine,
return armed;
/* Make the caller recheck if its request has already started. */
- set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
- return i915_seqno_passed(intel_engine_get_seqno(engine),
- wait->seqno - 1);
+ if (i915_seqno_passed(intel_engine_get_seqno(engine),
+ wait->seqno - 1)) {
+ set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
+ return true;
+ }
+
+ return false;
}
static inline bool chain_wakeup(struct rb_node *rb, int priority)
--
2.18.0
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