[PATCH 10/10] wip
José Roberto de Souza
jose.souza at intel.com
Sat Jul 21 01:24:05 UTC 2018
---
drivers/gpu/drm/i915/i915_drv.c | 110 ++++++++++++------
drivers/gpu/drm/i915/i915_irq.c | 142 +++++++++++++++--------
drivers/gpu/drm/i915/i915_suspend.c | 24 ++--
drivers/gpu/drm/i915/intel_device_info.c | 8 +-
drivers/gpu/drm/i915/intel_display.c | 2 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 74 +++++++++---
7 files changed, 249 insertions(+), 112 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 26a2734ffc3f..fca9fb2c940a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -879,6 +879,11 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
memcpy(device_info, match_info, sizeof(*device_info));
device_info->device_id = dev_priv->drm.pdev->device;
+ if (i915_modparams.disable_display) {
+ DRM_DEBUG_KMS("Setting num_pipes=0 as display is disabled\n");
+ device_info->num_pipes = 0;
+ }
+
BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
sizeof(device_info->platform_mask) * BITS_PER_BYTE);
BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
@@ -908,14 +913,18 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
intel_wopcm_init_early(&dev_priv->wopcm);
intel_uc_init_early(dev_priv);
intel_pm_setup(dev_priv);
- intel_init_dpio(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_init_dpio(dev_priv);
intel_power_domains_init(dev_priv);
intel_irq_init(dev_priv);
intel_hangcheck_init(dev_priv);
- intel_init_display_hooks(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
- intel_init_audio_hooks(dev_priv);
- intel_display_crc_init(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_init_audio_hooks(dev_priv);
+ intel_display_crc_init(dev_priv);
+ }
intel_detect_preproduction_hw(dev_priv);
@@ -1443,7 +1452,10 @@ void i915_driver_unload(struct drm_device *dev)
if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
- intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ else
+ intel_runtime_pm_get(dev_priv);//check if really need
if (INTEL_INFO(dev_priv)->num_pipes)
drm_atomic_helper_shutdown(dev);
@@ -1469,10 +1481,12 @@ void i915_driver_unload(struct drm_device *dev)
intel_bios_cleanup(dev_priv);
+ // TODO remove switcheroo
vga_switcheroo_unregister_client(pdev);
vga_client_register(pdev, NULL, NULL, NULL);
- intel_csr_ucode_fini(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_csr_ucode_fini(dev_priv);
/* Free error state after interrupts are fully disabled. */
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
@@ -1485,7 +1499,10 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_cleanup_hw(dev_priv);
i915_driver_cleanup_mmio(dev_priv);
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+ else
+ intel_runtime_pm_put(dev_priv);//check if really need
}
static void i915_driver_release(struct drm_device *dev)
@@ -1524,7 +1541,10 @@ static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
*/
static void i915_driver_lastclose(struct drm_device *dev)
{
- intel_fbdev_restore_mode(dev);
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_fbdev_restore_mode(dev);
vga_switcheroo_process_delayed_switch();
}
@@ -1592,22 +1612,29 @@ static int i915_drm_suspend(struct drm_device *dev)
disable_rpm_wakeref_asserts(dev_priv);
- /* We do a lot of poking in a lot of registers, make sure they work
- * properly. */
- intel_display_set_init_power(dev_priv, true);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ /* We do a lot of poking in a lot of registers, make sure they work
+ * properly. */
+ intel_display_set_init_power(dev_priv, true);
- drm_kms_helper_poll_disable(dev);
+ drm_kms_helper_poll_disable(dev);
+ }
pci_save_state(pdev);
- intel_display_suspend(dev);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_display_suspend(dev);
- intel_dp_mst_suspend(dev_priv);
+ intel_dp_mst_suspend(dev_priv);
+ }
intel_runtime_pm_disable_interrupts(dev_priv);
- intel_hpd_cancel_work(dev_priv);
- intel_suspend_encoders(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_hpd_cancel_work(dev_priv);
+
+ intel_suspend_encoders(dev_priv);
+ }
intel_suspend_hw(dev_priv);
@@ -1620,11 +1647,13 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_opregion_unregister(dev_priv);
- intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
dev_priv->suspend_count++;
- intel_csr_ucode_suspend(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_csr_ucode_suspend(dev_priv);
enable_rpm_wakeref_asserts(dev_priv);
@@ -1735,10 +1764,12 @@ static int i915_drm_resume(struct drm_device *dev)
if (ret)
DRM_ERROR("failed to re-enable GGTT\n");
- intel_csr_ucode_resume(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_csr_ucode_resume(dev_priv);
i915_restore_state(dev_priv);
- intel_pps_unlock_regs_wa(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_pps_unlock_regs_wa(dev_priv);
intel_opregion_setup(dev_priv);
intel_init_pch_refclk(dev_priv);
@@ -1755,11 +1786,13 @@ static int i915_drm_resume(struct drm_device *dev)
*/
intel_runtime_pm_enable_interrupts(dev_priv);
- drm_mode_config_reset(dev);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ drm_mode_config_reset(dev);
i915_gem_resume(dev_priv);
- intel_modeset_init_hw(dev);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_modeset_init_hw(dev);
intel_init_clock_gating(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
@@ -1767,23 +1800,26 @@ static int i915_drm_resume(struct drm_device *dev)
dev_priv->display.hpd_irq_setup(dev_priv);
spin_unlock_irq(&dev_priv->irq_lock);
- intel_dp_mst_resume(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_dp_mst_resume(dev_priv);
- intel_display_resume(dev);
+ intel_display_resume(dev);
- drm_kms_helper_poll_enable(dev);
+ drm_kms_helper_poll_enable(dev);
- /*
- * ... but also need to make sure that hotplug processing
- * doesn't cause havoc. Like in the driver load code we don't
- * bother with the tiny race here where we might loose hotplug
- * notifications.
- * */
- intel_hpd_init(dev_priv);
+ /*
+ * ... but also need to make sure that hotplug processing
+ * doesn't cause havoc. Like in the driver load code we don't
+ * bother with the tiny race here where we might loose hotplug
+ * notifications.
+ * */
+ intel_hpd_init(dev_priv);
+ }
intel_opregion_register(dev_priv);
- intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
intel_opregion_notify_adapter(dev_priv, PCI_D0);
@@ -1866,7 +1902,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
if (dev_priv->power_domains_suspended)
intel_power_domains_init_hw(dev_priv, true);
else
- intel_display_set_init_power(dev_priv, true);
+ intel_display_set_init_power(dev_priv, true);//??
intel_engines_sanitize(dev_priv);
@@ -2687,7 +2723,8 @@ static int intel_runtime_suspend(struct device *kdev)
assert_forcewakes_inactive(dev_priv);
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+ if (INTEL_INFO(dev_priv)->num_pipes && (!IS_VALLEYVIEW(dev_priv) &&
+ !IS_CHERRYVIEW(dev_priv)))
intel_hpd_poll_init(dev_priv);
DRM_DEBUG_KMS("Device suspended\n");
@@ -2744,7 +2781,8 @@ static int intel_runtime_resume(struct device *kdev)
* power well, so hpd is reinitialized from there. For
* everyone else do it here.
*/
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+ if (INTEL_INFO(dev_priv)->num_pipes && (!IS_VALLEYVIEW(dev_priv) &&
+ !IS_CHERRYVIEW(dev_priv)))
intel_hpd_init(dev_priv);
intel_enable_ipc(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5dadefca2ad2..7b9af6e1cd6c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3551,11 +3551,12 @@ static void ironlake_irq_reset(struct drm_device *dev)
if (IS_GEN5(dev_priv))
I915_WRITE(HWSTAM, 0xffffffff);
- GEN3_IRQ_RESET(DE);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ GEN3_IRQ_RESET(DE);
if (IS_GEN7(dev_priv))
I915_WRITE(GEN7_ERR_INT, 0xffffffff);
- if (IS_HASWELL(dev_priv)) {
+ if (IS_HASWELL(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
I915_WRITE(EDP_PSR_IMR, 0xffffffff);
I915_WRITE(EDP_PSR_IIR, 0xffffffff);
}
@@ -3574,6 +3575,9 @@ static void valleyview_irq_reset(struct drm_device *dev)
gen5_gt_irq_reset(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_reset(dev_priv);
@@ -3598,6 +3602,9 @@ static void gen8_irq_reset(struct drm_device *dev)
gen8_gt_irq_reset(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
I915_WRITE(EDP_PSR_IMR, 0xffffffff);
I915_WRITE(EDP_PSR_IIR, 0xffffffff);
@@ -3641,6 +3648,9 @@ static void gen11_irq_reset(struct drm_device *dev)
gen11_gt_irq_reset(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
for_each_pipe(dev_priv, pipe)
@@ -3709,6 +3719,9 @@ static void cherryview_irq_reset(struct drm_device *dev)
gen8_gt_irq_reset(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
GEN3_IRQ_RESET(GEN8_PCU_);
spin_lock_irq(&dev_priv->irq_lock);
@@ -4049,7 +4062,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
DE_DP_A_HOTPLUG);
}
- if (IS_HASWELL(dev_priv)) {
+ if (IS_HASWELL(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
@@ -4059,15 +4072,17 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
ibx_irq_pre_postinstall(dev);
- GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
gen5_gt_irq_postinstall(dev);
- ilk_hpd_detection_setup(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ ilk_hpd_detection_setup(dev_priv);
ibx_irq_postinstall(dev);
- if (IS_IRONLAKE_M(dev_priv)) {
+ if (IS_IRONLAKE_M(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
/* Enable PCU event interrupts
*
* spinlocking not required here for correctness since interrupt
@@ -4116,10 +4131,12 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
gen5_gt_irq_postinstall(dev);
- spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->display_irqs_enabled)
- vlv_display_irq_postinstall(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (dev_priv->display_irqs_enabled)
+ vlv_display_irq_postinstall(dev_priv);
+ spin_unlock_irq(&dev_priv->irq_lock);
+ }
I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
POSTING_READ(VLV_MASTER_IER);
@@ -4234,7 +4251,8 @@ static int gen8_irq_postinstall(struct drm_device *dev)
ibx_irq_pre_postinstall(dev);
gen8_gt_irq_postinstall(dev_priv);
- gen8_de_irq_postinstall(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ gen8_de_irq_postinstall(dev_priv);
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev);
@@ -4296,11 +4314,13 @@ static int gen11_irq_postinstall(struct drm_device *dev)
icp_irq_postinstall(dev);
gen11_gt_irq_postinstall(dev_priv);
- gen8_de_irq_postinstall(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ gen8_de_irq_postinstall(dev_priv);
GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
- I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
POSTING_READ(GEN11_GFX_MSTR_IRQ);
@@ -4314,10 +4334,12 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
gen8_gt_irq_postinstall(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->display_irqs_enabled)
- vlv_display_irq_postinstall(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (dev_priv->display_irqs_enabled)
+ vlv_display_irq_postinstall(dev_priv);
+ spin_unlock_irq(&dev_priv->irq_lock);
+ }
I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
POSTING_READ(GEN8_MASTER_IRQ);
@@ -4329,7 +4351,8 @@ static void i8xx_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- i9xx_pipestat_irq_reset(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ i9xx_pipestat_irq_reset(dev_priv);
I915_WRITE16(HWSTAM, 0xffff);
@@ -4339,7 +4362,7 @@ static void i8xx_irq_reset(struct drm_device *dev)
static int i8xx_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- u16 enable_mask;
+ u16 enable_mask = I915_MASTER_ERROR_INTERRUPT | I915_USER_INTERRUPT;
I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
I915_ERROR_MEMORY_REFRESH));
@@ -4350,14 +4373,15 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
I915_MASTER_ERROR_INTERRUPT);
- enable_mask =
- I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_MASTER_ERROR_INTERRUPT |
- I915_USER_INTERRUPT;
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+ I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return 0;
+
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
spin_lock_irq(&dev_priv->irq_lock);
@@ -4493,12 +4517,15 @@ static void i915_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (I915_HAS_HOTPLUG(dev_priv)) {
- i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
- I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
- }
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (I915_HAS_HOTPLUG(dev_priv)) {
+ i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
+ I915_WRITE(PORT_HOTPLUG_STAT,
+ I915_READ(PORT_HOTPLUG_STAT));
+ }
- i9xx_pipestat_irq_reset(dev_priv);
+ i9xx_pipestat_irq_reset(dev_priv);
+ }
I915_WRITE(HWSTAM, 0xffffffff);
@@ -4508,7 +4535,8 @@ static void i915_irq_reset(struct drm_device *dev)
static int i915_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- u32 enable_mask;
+ u32 enable_mask = I915_MASTER_ERROR_INTERRUPT |
+ I915_USER_INTERRUPT;
I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
I915_ERROR_MEMORY_REFRESH));
@@ -4520,14 +4548,12 @@ static int i915_irq_postinstall(struct drm_device *dev)
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
I915_MASTER_ERROR_INTERRUPT);
- enable_mask =
- I915_ASLE_INTERRUPT |
- I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_MASTER_ERROR_INTERRUPT |
- I915_USER_INTERRUPT;
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ enable_mask |= I915_ASLE_INTERRUPT |
+ I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+ I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (INTEL_INFO(dev_priv)->num_pipes && I915_HAS_HOTPLUG(dev_priv)) {
/* Enable in IER... */
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
/* and unmask in IMR */
@@ -4536,6 +4562,9 @@ static int i915_irq_postinstall(struct drm_device *dev)
GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return 0;
+
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
spin_lock_irq(&dev_priv->irq_lock);
@@ -4606,10 +4635,12 @@ static void i965_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
- I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
+ I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
- i9xx_pipestat_irq_reset(dev_priv);
+ i9xx_pipestat_irq_reset(dev_priv);
+ }
I915_WRITE(HWSTAM, 0xffffffff);
@@ -4619,7 +4650,7 @@ static void i965_irq_reset(struct drm_device *dev)
static int i965_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- u32 enable_mask;
+ u32 enable_mask = I915_MASTER_ERROR_INTERRUPT | I915_USER_INTERRUPT;
u32 error_mask;
/*
@@ -4645,19 +4676,22 @@ static int i965_irq_postinstall(struct drm_device *dev)
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
I915_MASTER_ERROR_INTERRUPT);
- enable_mask =
- I915_ASLE_INTERRUPT |
- I915_DISPLAY_PORT_INTERRUPT |
- I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
- I915_MASTER_ERROR_INTERRUPT |
- I915_USER_INTERRUPT;
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ enable_mask |=
+ I915_ASLE_INTERRUPT |
+ I915_DISPLAY_PORT_INTERRUPT |
+ I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+ I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+ }
if (IS_G4X(dev_priv))
enable_mask |= I915_BSD_USER_INTERRUPT;
GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return 0;
+
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
spin_lock_irq(&dev_priv->irq_lock);
@@ -4765,7 +4799,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
struct intel_rps *rps = &dev_priv->gt_pm.rps;
int i;
- intel_hpd_init_work(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_hpd_init_work(dev_priv);
INIT_WORK(&rps->work, gen6_pm_rps_work);
@@ -4903,6 +4938,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
}
+
+ if (!INTEL_INFO(dev_priv)->num_pipes) {
+ dev->driver->enable_vblank = NULL;
+ dev->driver->disable_vblank = NULL;
+ dev_priv->display.hpd_irq_setup = NULL;
+ }
}
/**
@@ -4952,7 +4993,8 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
drm_irq_uninstall(&dev_priv->drm);
- intel_hpd_cancel_work(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_hpd_cancel_work(dev_priv);
dev_priv->runtime_pm.irqs_enabled = false;
}
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 8f3aa4dc0c98..f697865236a6 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -63,11 +63,13 @@ int i915_save_state(struct drm_i915_private *dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
- i915_save_display(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ i915_save_display(dev_priv);
- if (IS_GEN4(dev_priv))
- pci_read_config_word(pdev, GCDGMBUS,
- &dev_priv->regfile.saveGCDGMBUS);
+ if (IS_GEN4(dev_priv))
+ pci_read_config_word(pdev, GCDGMBUS,
+ &dev_priv->regfile.saveGCDGMBUS);
+ }
/* Cache mode state */
if (INTEL_GEN(dev_priv) < 7)
@@ -108,10 +110,13 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
- if (IS_GEN4(dev_priv))
- pci_write_config_word(pdev, GCDGMBUS,
- dev_priv->regfile.saveGCDGMBUS);
- i915_restore_display(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (IS_GEN4(dev_priv))
+ pci_write_config_word(pdev, GCDGMBUS,
+ dev_priv->regfile.saveGCDGMBUS);
+
+ i915_restore_display(dev_priv);
+ }
/* Cache mode state */
if (INTEL_GEN(dev_priv) < 7)
@@ -143,7 +148,8 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
mutex_unlock(&dev_priv->drm.struct_mutex);
- intel_i2c_reset(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_i2c_reset(dev_priv);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0ef0c6448d53..81c613ca44d9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -776,10 +776,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
info->num_sprites[pipe] = 1;
}
- if (i915_modparams.disable_display) {
- DRM_INFO("Display disabled (module parameter)\n");
- info->num_pipes = 0;
- } else if (info->num_pipes > 0 &&
+
+ if (info->num_pipes > 0 &&
(IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
@@ -835,6 +833,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
disabled_mask);
else
info->num_pipes -= num_bits;
+ } else {
+ DRM_DEBUG_KMS("else in intel_device_info_runtime_init() info->num_pipes=%d\n", info->num_pipes);
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d1dcd9d4a682..83e085922dde 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3782,6 +3782,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
return;
+ WARN_ON(!INTEL_INFO(dev_priv)->num_pipes);
+
state = fetch_and_zero(&dev_priv->modeset_restore_state);
if (!state)
goto unlock;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 949e1fd7da77..ed48b3a12166 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9251,6 +9251,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN5(dev_priv))
i915_ironlake_get_mem_freq(dev_priv);
+ // this stuff makes sense here?
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index fb12df402d21..0c73e5163272 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -796,6 +796,9 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -982,6 +985,8 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
struct intel_encoder *encoder;
enum pipe pipe;
+ // TODO no need to run that
+
/*
* Enable the CRI clock source so we can get at the
* display and the reference clock for VGA
@@ -1038,7 +1043,8 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
intel_power_sequencer_reset(dev_priv);
/* Prevent us from re-enabling polling on accident in late suspend */
- if (!dev_priv->drm.dev->power.is_suspended)
+ if (INTEL_INFO(dev_priv)->num_pipes &&
+ !dev_priv->drm.dev->power.is_suspended)
intel_hpd_poll_init(dev_priv);
}
@@ -2915,11 +2921,11 @@ void intel_power_domains_fini(struct drm_i915_private *dev_priv)
* intel_runtime_pm_enable(). We have to hand back the control of the
* device to the core with this reference held.
*/
- intel_display_set_init_power(dev_priv, true);
+ //intel_display_set_init_power(dev_priv, true);
/* Remove the refcount we took to keep power well support disabled. */
- if (!i915_modparams.disable_power_well)
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+ /*if (!i915_modparams.disable_power_well)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);*/
/*
* Remove the refcount we took in intel_runtime_pm_enable() in case
@@ -3082,6 +3088,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
skl_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -3097,10 +3106,14 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_dbuf_cdclk;
+
gen9_dbuf_disable(dev_priv);
skl_uninit_cdclk(dev_priv);
+skip_dbuf_cdclk:
/* The spec doesn't call for removing the reset handshake flag */
/* disable PG1 and Misc I/O */
@@ -3144,6 +3157,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
bxt_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -3159,12 +3175,16 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_dbuf_cdclk;
+
gen9_dbuf_disable(dev_priv);
bxt_uninit_cdclk(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
+skip_dbuf_cdclk:
/*
* Disable PW1 (PG1).
* Note that even though the driver's request is removed power well 1
@@ -3257,6 +3277,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* 1. Enable PCH Reset Handshake */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_ports_init;
+
/* 2. Enable Comp */
val = I915_READ(CHICKEN_MISC_2);
val &= ~CNL_COMP_PWR_DOWN;
@@ -3274,6 +3297,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
val |= CL_POWER_DOWN_ENABLE;
I915_WRITE(CNL_PORT_CL1CM_DW5, val);
+skip_ports_init:
/*
* 4. Enable Power Well 1 (PG1).
* The AUX IO power wells will be enabled on demand.
@@ -3283,6 +3307,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
intel_power_well_enable(dev_priv, well);
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 5. Enable CD clock */
cnl_init_cdclk(dev_priv);
@@ -3301,7 +3328,10 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ /* 1. Disable all display engine functions -> already done */
+
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_dbuf_cdclk;
/* 2. Disable DBUF */
gen9_dbuf_disable(dev_priv);
@@ -3309,6 +3339,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
/* 3. Disable CD clock */
cnl_uninit_cdclk(dev_priv);
+skip_dbuf_cdclk:
/*
* 4. Disable Power Well 1 (PG1).
* The AUX IO power wells are toggled on demand, so they are already
@@ -3321,6 +3352,9 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 5. Disable Comp */
val = I915_READ(CHICKEN_MISC_2);
val |= CNL_COMP_PWR_DOWN;
@@ -3340,6 +3374,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
/* 1. Enable PCH reset handshake. */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_ports_init;
+
for (port = PORT_A; port <= PORT_B; port++) {
/* 2. Enable DDI combo PHY comp. */
val = I915_READ(ICL_PHY_MISC(port));
@@ -3358,6 +3395,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
I915_WRITE(ICL_PORT_CL_DW5(port), val);
}
+skip_ports_init:
/*
* 4. Enable Power Well 1 (PG1).
* The AUX IO power wells will be enabled on demand.
@@ -3367,6 +3405,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_power_well_enable(dev_priv, well);
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 5. Enable CDCLK. */
icl_init_cdclk(dev_priv);
@@ -3390,7 +3431,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ /* 1. Disable all display engine functions -> already done */
+
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_dbuf_cdclk;
/* 2. Disable DBUF */
icl_dbuf_disable(dev_priv);
@@ -3398,6 +3442,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
/* 3. Disable CD clock */
icl_uninit_cdclk(dev_priv);
+skip_dbuf_cdclk:
/*
* 4. Disable Power Well 1 (PG1).
* The AUX IO power wells are toggled on demand, so they are already
@@ -3408,6 +3453,9 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
intel_power_well_disable(dev_priv, well);
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 5. Disable Comp */
for (port = PORT_A; port <= PORT_B; port++) {
val = I915_READ(ICL_PHY_MISC(port));
@@ -3556,21 +3604,21 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
skl_display_core_init(dev_priv, resume);
} else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
- } else if (IS_CHERRYVIEW(dev_priv)) {
+ } else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(&power_domains->lock);
chv_phy_control_init(dev_priv);
mutex_unlock(&power_domains->lock);
- } else if (IS_VALLEYVIEW(dev_priv)) {
+ } else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(&power_domains->lock);
vlv_cmnlane_wa(dev_priv);
mutex_unlock(&power_domains->lock);
}
/* For now, we need the power well to be always enabled. */
- intel_display_set_init_power(dev_priv, true);
+ //intel_display_set_init_power(dev_priv, true);
/* Disable power support if the user asked so. */
- if (!i915_modparams.disable_power_well)
- intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ /*if (!i915_modparams.disable_power_well)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);*/
intel_power_domains_sync_hw(dev_priv);
power_domains->initializing = false;
}
@@ -3588,8 +3636,8 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
* Even if power well support was disabled we still want to disable
* power wells while we are system suspended.
*/
- if (!i915_modparams.disable_power_well)
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+ /*if (!i915_modparams.disable_power_well)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);*/
if (IS_ICELAKE(dev_priv))
icl_display_core_uninit(dev_priv);
--
2.18.0
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