[PATCH 11/13] divide by zero fix
José Roberto de Souza
jose.souza at intel.com
Tue Jul 24 20:03:03 UTC 2018
---
drivers/gpu/drm/i915/i915_gem.c | 13 +++++++++++++
drivers/gpu/drm/i915/intel_display.c | 12 ------------
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8b52cb768a67..94f07708166f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5461,6 +5461,17 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
goto out_ctx;
}
+static void intel_update_czclk(struct drm_i915_private *dev_priv)
+{
+ if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
+ return;
+
+ dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
+ CCK_CZ_CLOCK_CONTROL);
+
+ DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
+}
+
int i915_gem_init(struct drm_i915_private *dev_priv)
{
int ret;
@@ -5519,6 +5530,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto err_context;
}
+ intel_update_czclk(dev_priv);
+
intel_init_gt_powersave(dev_priv);
ret = intel_uc_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d1dcd9d4a682..371ec75a582a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -218,17 +218,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
dev_priv->hpll_freq);
}
-static void intel_update_czclk(struct drm_i915_private *dev_priv)
-{
- if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
- return;
-
- dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
- CCK_CZ_CLOCK_CONTROL);
-
- DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
-}
-
static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *pipe_config)
@@ -15246,7 +15235,6 @@ int intel_modeset_init(struct drm_device *dev)
intel_shared_dpll_init(dev);
intel_update_fdi_pll_freq(dev_priv);
- intel_update_czclk(dev_priv);
intel_modeset_init_hw(dev);
if (dev_priv->max_cdclk_freq == 0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 949e1fd7da77..2682374e0fee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7361,6 +7361,8 @@ static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
CCK_GPLL_CLOCK_CONTROL,
dev_priv->czclk_freq);
+ WARN_ON(dev_priv->gt_pm.rps.gpll_ref_freq == 0);
+
DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
dev_priv->gt_pm.rps.gpll_ref_freq);
}
@@ -9551,6 +9553,8 @@ static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ WARN_ON(rps->gpll_ref_freq == 0);
+
return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
}
@@ -9569,6 +9573,8 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ WARN_ON(rps->gpll_ref_freq == 0);
+
/* CHV needs even values */
return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
}
--
2.18.0
More information about the Intel-gfx-trybot
mailing list