[PATCH 17/17] wip
José Roberto de Souza
jose.souza at intel.com
Wed Jul 25 00:54:06 UTC 2018
---
drivers/gpu/drm/i915/i915_drv.c | 63 ++++++++++++++++----
drivers/gpu/drm/i915/intel_device_info.c | 8 +--
drivers/gpu/drm/i915/intel_display.c | 5 +-
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 75 +++++++++++++++++++++---
5 files changed, 125 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 47feea315906..ee9281f4572d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -876,6 +876,11 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
memcpy(device_info, match_info, sizeof(*device_info));
device_info->device_id = dev_priv->drm.pdev->device;
+ if (i915_modparams.disable_display) {
+ DRM_DEBUG_KMS("Setting num_pipes=0 as display is disabled\n");
+ device_info->num_pipes = 0;
+ }
+
BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
sizeof(device_info->platform_mask) * BITS_PER_BYTE);
BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
@@ -905,14 +910,18 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
intel_wopcm_init_early(&dev_priv->wopcm);
intel_uc_init_early(dev_priv);
intel_pm_setup(dev_priv);
- intel_init_dpio(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_init_dpio(dev_priv);
intel_power_domains_init(dev_priv);
intel_irq_init(dev_priv);
intel_hangcheck_init(dev_priv);
- intel_init_display_hooks(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
- intel_init_audio_hooks(dev_priv);
- intel_display_crc_init(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_init_audio_hooks(dev_priv);
+ intel_display_crc_init(dev_priv);
+ }
intel_detect_preproduction_hw(dev_priv);
@@ -1396,6 +1405,17 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
goto cleanup_gem;
}
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_display_set_init_power(dev_priv, false);
+ /* only checking power domains when num_pipe > 0 because BIOS
+ * could be the one holding power wells enabled causing error
+ * messages.
+ */
+ intel_power_domains_verify_state(dev_priv);
+ } else
+ intel_runtime_pm_put(dev_priv);
+
+
i915_driver_register(dev_priv);
intel_runtime_pm_enable(dev_priv);
@@ -1443,7 +1463,10 @@ void i915_driver_unload(struct drm_device *dev)
if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
- intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ else
+ intel_runtime_pm_get(dev_priv);
if (INTEL_INFO(dev_priv)->num_pipes)
drm_atomic_helper_shutdown(dev);
@@ -1469,6 +1492,7 @@ void i915_driver_unload(struct drm_device *dev)
intel_bios_cleanup(dev_priv);
+ // TODO remove switcheroo
vga_switcheroo_unregister_client(pdev);
vga_client_register(pdev, NULL, NULL, NULL);
@@ -1486,7 +1510,10 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_cleanup_hw(dev_priv);
i915_driver_cleanup_mmio(dev_priv);
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+ else
+ intel_runtime_pm_put(dev_priv);
}
static void i915_driver_release(struct drm_device *dev)
@@ -1598,11 +1625,13 @@ static int i915_drm_suspend(struct drm_device *dev)
/* We do a lot of poking in a lot of registers, make sure they work
* properly. */
- intel_display_set_init_power(dev_priv, true);
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_display_set_init_power(dev_priv, true);
+ else
+ intel_runtime_pm_get(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
drm_kms_helper_poll_disable(dev);
- }
pci_save_state(pdev);
@@ -1654,7 +1683,10 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
i915_gem_suspend_late(dev_priv);
- intel_display_set_init_power(dev_priv, false);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_display_set_init_power(dev_priv, false);
+ else
+ intel_runtime_pm_put(dev_priv);
intel_uncore_suspend(dev_priv);
/*
@@ -1775,7 +1807,8 @@ static int i915_drm_resume(struct drm_device *dev)
i915_gem_resume(dev_priv);
- intel_modeset_init_hw(dev);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_modeset_init_hw(dev);
intel_init_clock_gating(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
@@ -1884,8 +1917,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
if (dev_priv->power_domains_suspended)
intel_power_domains_init_hw(dev_priv, true);
- else
- intel_display_set_init_power(dev_priv, true);
+ else {
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_display_set_init_power(dev_priv, true);
+ else
+ intel_runtime_pm_get(dev_priv);
+ }
intel_engines_sanitize(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0ef0c6448d53..81c613ca44d9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -776,10 +776,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
info->num_sprites[pipe] = 1;
}
- if (i915_modparams.disable_display) {
- DRM_INFO("Display disabled (module parameter)\n");
- info->num_pipes = 0;
- } else if (info->num_pipes > 0 &&
+
+ if (info->num_pipes > 0 &&
(IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
@@ -835,6 +833,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
disabled_mask);
else
info->num_pipes -= num_bits;
+ } else {
+ DRM_DEBUG_KMS("else in intel_device_info_runtime_init() info->num_pipes=%d\n", info->num_pipes);
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 371ec75a582a..fd6853f19326 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3771,6 +3771,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
return;
+ WARN_ON(!INTEL_INFO(dev_priv)->num_pipes);
+
state = fetch_and_zero(&dev_priv->modeset_restore_state);
if (!state)
goto unlock;
@@ -15867,9 +15869,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
}
- intel_display_set_init_power(dev_priv, false);
-
- intel_power_domains_verify_state(dev_priv);
intel_fbc_init_pipe_state(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2682374e0fee..66bf2b780baa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9253,6 +9253,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN5(dev_priv))
i915_ironlake_get_mem_freq(dev_priv);
+ // this stuff makes sense here?
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a43acd979f47..23d5c4c9d8ea 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -273,6 +273,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
if (dev_priv->power_domains.init_power_on == enable)
return;
+ //dump_stack();
+
if (enable)
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
else
@@ -796,6 +798,9 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -982,6 +987,8 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
struct intel_encoder *encoder;
enum pipe pipe;
+ // TODO no need to run that
+
/*
* Enable the CRI clock source so we can get at the
* display and the reference clock for VGA
@@ -1541,6 +1548,8 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *power_well;
+ WARN_ON(!INTEL_INFO(dev_priv)->num_pipes && domain != POWER_DOMAIN_GT_IRQ);
+
for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
intel_power_well_get(dev_priv, power_well);
@@ -1626,8 +1635,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
struct i915_power_domains *power_domains;
struct i915_power_well *power_well;
+ DRM_DEBUG_KMS("intel_display_power_put() domain=%d\n", domain);
+
power_domains = &dev_priv->power_domains;
+ WARN_ON(!INTEL_INFO(dev_priv)->num_pipes && domain != POWER_DOMAIN_GT_IRQ);
+
mutex_lock(&power_domains->lock);
WARN(!power_domains->domain_use_count[domain],
@@ -2916,7 +2929,10 @@ void intel_power_domains_fini(struct drm_i915_private *dev_priv)
* intel_runtime_pm_enable(). We have to hand back the control of the
* device to the core with this reference held.
*/
- intel_display_set_init_power(dev_priv, true);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_display_set_init_power(dev_priv, true);
+ else
+ intel_runtime_pm_get(dev_priv);
/* Remove the refcount we took to keep power well support disabled. */
if (!i915_modparams.disable_power_well)
@@ -3083,6 +3099,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
skl_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -3098,10 +3117,14 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_dbuf_cdclk;
+
gen9_dbuf_disable(dev_priv);
skl_uninit_cdclk(dev_priv);
+skip_dbuf_cdclk:
/* The spec doesn't call for removing the reset handshake flag */
/* disable PG1 and Misc I/O */
@@ -3145,6 +3168,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
bxt_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -3160,12 +3186,16 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_dbuf_cdclk;
+
gen9_dbuf_disable(dev_priv);
bxt_uninit_cdclk(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
+skip_dbuf_cdclk:
/*
* Disable PW1 (PG1).
* Note that even though the driver's request is removed power well 1
@@ -3258,6 +3288,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* 1. Enable PCH Reset Handshake */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_ports_init;
+
/* 2. Enable Comp */
val = I915_READ(CHICKEN_MISC_2);
val &= ~CNL_COMP_PWR_DOWN;
@@ -3275,6 +3308,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
val |= CL_POWER_DOWN_ENABLE;
I915_WRITE(CNL_PORT_CL1CM_DW5, val);
+skip_ports_init:
/*
* 4. Enable Power Well 1 (PG1).
* The AUX IO power wells will be enabled on demand.
@@ -3284,6 +3318,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
intel_power_well_enable(dev_priv, well);
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 5. Enable CD clock */
cnl_init_cdclk(dev_priv);
@@ -3302,7 +3339,10 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ /* 1. Disable all display engine functions -> already done */
+
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_dbuf_cdclk;
/* 2. Disable DBUF */
gen9_dbuf_disable(dev_priv);
@@ -3310,6 +3350,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
/* 3. Disable CD clock */
cnl_uninit_cdclk(dev_priv);
+skip_dbuf_cdclk:
/*
* 4. Disable Power Well 1 (PG1).
* The AUX IO power wells are toggled on demand, so they are already
@@ -3322,6 +3363,9 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 5. Disable Comp */
val = I915_READ(CHICKEN_MISC_2);
val |= CNL_COMP_PWR_DOWN;
@@ -3341,6 +3385,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
/* 1. Enable PCH reset handshake. */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_ports_init;
+
for (port = PORT_A; port <= PORT_B; port++) {
/* 2. Enable DDI combo PHY comp. */
val = I915_READ(ICL_PHY_MISC(port));
@@ -3359,6 +3406,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
I915_WRITE(ICL_PORT_CL_DW5(port), val);
}
+skip_ports_init:
/*
* 4. Enable Power Well 1 (PG1).
* The AUX IO power wells will be enabled on demand.
@@ -3368,6 +3416,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_power_well_enable(dev_priv, well);
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 5. Enable CDCLK. */
icl_init_cdclk(dev_priv);
@@ -3391,7 +3442,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ /* 1. Disable all display engine functions -> already done */
+
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ goto skip_dbuf_cdclk;
/* 2. Disable DBUF */
icl_dbuf_disable(dev_priv);
@@ -3399,6 +3453,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
/* 3. Disable CD clock */
icl_uninit_cdclk(dev_priv);
+skip_dbuf_cdclk:
/*
* 4. Disable Power Well 1 (PG1).
* The AUX IO power wells are toggled on demand, so they are already
@@ -3409,6 +3464,9 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
intel_power_well_disable(dev_priv, well);
mutex_unlock(&power_domains->lock);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 5. Disable Comp */
for (port = PORT_A; port <= PORT_B; port++) {
val = I915_READ(ICL_PHY_MISC(port));
@@ -3557,18 +3615,21 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
skl_display_core_init(dev_priv, resume);
} else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
- } else if (IS_CHERRYVIEW(dev_priv)) {
+ } else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(&power_domains->lock);
chv_phy_control_init(dev_priv);
mutex_unlock(&power_domains->lock);
- } else if (IS_VALLEYVIEW(dev_priv)) {
+ } else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(&power_domains->lock);
vlv_cmnlane_wa(dev_priv);
mutex_unlock(&power_domains->lock);
}
- /* For now, we need the power well to be always enabled. */
- intel_display_set_init_power(dev_priv, true);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ /* For now, we need the power well to be always enabled. */
+ intel_display_set_init_power(dev_priv, true);
+ else
+ intel_runtime_pm_get(dev_priv);
/* Disable power support if the user asked so. */
if (!i915_modparams.disable_power_well)
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
--
2.18.0
More information about the Intel-gfx-trybot
mailing list