[PATCH 17/17] debug

[José Roberto de Souza]

---
 drivers/gpu/drm/i915/intel_fbc.c        | 1 +
 drivers/gpu/drm/i915/intel_pm.c         | 6 ++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 01d1d2088f04..4bfd6d0b3236 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -955,6 +955,7 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 	if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 		return;
 
+	WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0);
 	mutex_lock(&fbc->lock);
 
 	fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5cee42a4ef48..d44870b0e893 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7361,6 +7361,8 @@ static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
 				  CCK_GPLL_CLOCK_CONTROL,
 				  dev_priv->czclk_freq);
 
+	WARN_ON(dev_priv->gt_pm.rps.gpll_ref_freq == 0);
+
 	DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
 			 dev_priv->gt_pm.rps.gpll_ref_freq);
 }
@@ -9561,6 +9563,8 @@ static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
+	WARN_ON(rps->gpll_ref_freq == 0);
+
 	return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
 }
 
@@ -9579,6 +9583,8 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
+	WARN_ON(rps->gpll_ref_freq == 0);
+
 	/* CHV needs even values */
 	return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
 }
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a43acd979f47..3c8b5953fcfa 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -971,7 +971,7 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 	I915_WRITE(CBR1_VLV, 0);
 
-	WARN_ON(dev_priv->rawclk_freq == 0);
+	WARN_ON(INTEL_INFO(dev_priv)->num_pipes && dev_priv->rawclk_freq == 0);
 
 	I915_WRITE(RAWCLK_FREQ_VLV,
 		   DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
-- 
2.18.0