[PATCH 17/21] core_init/uninit

[José Roberto de Souza]

squah core_init
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 39 ++++++++++++++++++++++---
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4a0db54678a3..19ecd5787946 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3082,6 +3082,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 	/* enable PCH reset handshake */
 	skl_pch_reset_handshake(dev_priv);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	/* enable PG1 and Misc I/O */
 	mutex_lock(&power_domains->lock);
 
@@ -3107,6 +3110,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 	struct i915_power_well *well;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
 
 	gen9_dbuf_disable(dev_priv);
 
@@ -3155,6 +3160,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 
 	mutex_unlock(&power_domains->lock);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	bxt_init_cdclk(dev_priv);
 
 	gen9_dbuf_enable(dev_priv);
@@ -3170,12 +3178,16 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		goto skip_dbuf_cdclk;
+
 	gen9_dbuf_disable(dev_priv);
 
 	bxt_uninit_cdclk(dev_priv);
 
 	/* The spec doesn't call for removing the reset handshake flag */
 
+skip_dbuf_cdclk:
 	/*
 	 * Disable PW1 (PG1).
 	 * Note that even though the driver's request is removed power well 1
@@ -3268,6 +3280,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 	/* 1. Enable PCH Reset Handshake */
 	skl_pch_reset_handshake(dev_priv);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	/* 2. Enable Comp */
 	val = I915_READ(CHICKEN_MISC_2);
 	val &= ~CNL_COMP_PWR_DOWN;
@@ -3312,7 +3327,10 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* 1. Disable all display engine functions -> aready done */
+	/* 1. Disable all display engine functions -> already done */
+
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
 
 	/* 2. Disable DBUF */
 	gen9_dbuf_disable(dev_priv);
@@ -3351,6 +3369,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	/* 1. Enable PCH reset handshake. */
 	skl_pch_reset_handshake(dev_priv);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	for (port = PORT_A; port <= PORT_B; port++) {
 		/* 2. Enable DDI combo PHY comp. */
 		val = I915_READ(ICL_PHY_MISC(port));
@@ -3397,7 +3418,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* 1. Disable all display engine functions -> aready done */
+	/* 1. Disable all display engine functions -> already done */
+
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
 
 	/* 2. Disable DBUF */
 	icl_dbuf_disable(dev_priv);
@@ -3563,21 +3587,28 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 		skl_display_core_init(dev_priv, resume);
 	} else if (IS_GEN9_LP(dev_priv)) {
 		bxt_display_core_init(dev_priv, resume);
-	} else if (IS_CHERRYVIEW(dev_priv)) {
+	} else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
 		mutex_lock(&power_domains->lock);
 		chv_phy_control_init(dev_priv);
 		mutex_unlock(&power_domains->lock);
-	} else if (IS_VALLEYVIEW(dev_priv)) {
+	} else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
 		mutex_lock(&power_domains->lock);
 		vlv_cmnlane_wa(dev_priv);
 		mutex_unlock(&power_domains->lock);
 	}
 
+	if (!INTEL_INFO(dev_priv)->num_pipes) {
+		intel_runtime_pm_get(dev_priv);
+		goto end;
+	}
+
 	/* For now, we need the power well to be always enabled. */
 	intel_display_set_init_power(dev_priv, true);
 	/* Disable power support if the user asked so. */
 	if (!i915_modparams.disable_power_well)
 		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+
+end:
 	intel_power_domains_sync_hw(dev_priv);
 	power_domains->initializing = false;
 }
-- 
2.18.0