[PATCH 15/22] debug

[José Roberto de Souza]

---
 drivers/gpu/drm/i915/i915_drv.c          |  5 +++++
 drivers/gpu/drm/i915/intel_device_info.c |  8 ++++----
 drivers/gpu/drm/i915/intel_runtime_pm.c  | 12 +++++++++++-
 3 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fc16cf4cecba..3ac520fab7a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -878,6 +878,11 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 	memcpy(device_info, match_info, sizeof(*device_info));
 	device_info->device_id = dev_priv->drm.pdev->device;
 
+	if (i915_modparams.disable_display) {
+		DRM_DEBUG_KMS("Setting num_pipes=0 as display is disabled\n");
+		device_info->num_pipes = 0;
+	}
+
 	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 		     sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0ef0c6448d53..81c613ca44d9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -776,10 +776,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 			info->num_sprites[pipe] = 1;
 	}
 
-	if (i915_modparams.disable_display) {
-		DRM_INFO("Display disabled (module parameter)\n");
-		info->num_pipes = 0;
-	} else if (info->num_pipes > 0 &&
+
+	if (info->num_pipes > 0 &&
 		   (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
 		   HAS_PCH_SPLIT(dev_priv)) {
 		u32 fuse_strap = I915_READ(FUSE_STRAP);
@@ -835,6 +833,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 				  disabled_mask);
 		else
 			info->num_pipes -= num_bits;
+	} else {
+		DRM_DEBUG_KMS("else in intel_device_info_runtime_init() info->num_pipes=%d\n", info->num_pipes);
 	}
 
 	/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 86f000d15a9c..4a0db54678a3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -971,7 +971,7 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 	I915_WRITE(CBR1_VLV, 0);
 
-	WARN_ON(dev_priv->rawclk_freq == 0);
+	WARN_ON(INTEL_INFO(dev_priv)->num_pipes && dev_priv->rawclk_freq == 0);
 
 	I915_WRITE(RAWCLK_FREQ_VLV,
 		   DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
@@ -982,6 +982,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 	struct intel_encoder *encoder;
 	enum pipe pipe;
 
+	// TODO no need to run that
+
+	WARN_ON(!INTEL_INFO(dev_priv)->num_pipes);
+
 	/*
 	 * Enable the CRI clock source so we can get at the
 	 * display and the reference clock for VGA
@@ -1541,6 +1545,8 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *power_well;
 
+	WARN_ON(!INTEL_INFO(dev_priv)->num_pipes && domain != POWER_DOMAIN_GT_IRQ);
+
 	for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
 		intel_power_well_get(dev_priv, power_well);
 
@@ -1626,8 +1632,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	struct i915_power_domains *power_domains;
 	struct i915_power_well *power_well;
 
+	DRM_DEBUG_KMS("intel_display_power_put() domain=%d\n", domain);
+
 	power_domains = &dev_priv->power_domains;
 
+	WARN_ON(!INTEL_INFO(dev_priv)->num_pipes && domain != POWER_DOMAIN_GT_IRQ);
+
 	mutex_lock(&power_domains->lock);
 
 	WARN(!power_domains->domain_use_count[domain],
-- 
2.18.0