[PATCH 18/22] power well

[José Roberto de Souza]

squash power well
---
 drivers/gpu/drm/i915/i915_drv.c         | 39 +++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++--
 2 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0c55b91a5e50..af12f0372d3b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1406,6 +1406,16 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 			goto cleanup_gem;
 	}
 
+	if (INTEL_INFO(dev_priv)->num_pipes) {
+		intel_display_set_init_power(dev_priv, false);
+		/* only checking power domains when num_pipe > 0 because BIOS
+		 * could be the one holding power wells enabled causing error
+		 * messages.
+		 */
+		intel_power_domains_verify_state(dev_priv);
+	} else
+		intel_runtime_pm_put(dev_priv);
+
 	i915_driver_register(dev_priv);
 
 	intel_runtime_pm_enable(dev_priv);
@@ -1465,7 +1475,10 @@ void i915_driver_unload(struct drm_device *dev)
 	if (i915_gem_suspend(dev_priv))
 		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 
-	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+	else
+		intel_runtime_pm_get(dev_priv);
 
 	if (INTEL_INFO(dev_priv)->num_pipes)
 		drm_atomic_helper_shutdown(dev);
@@ -1503,7 +1516,10 @@ void i915_driver_unload(struct drm_device *dev)
 	i915_driver_cleanup_hw(dev_priv);
 	i915_driver_cleanup_mmio(dev_priv);
 
-	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
+	else
+		intel_runtime_pm_put(dev_priv);
 }
 
 static void i915_driver_release(struct drm_device *dev)
@@ -1616,7 +1632,11 @@ static int i915_drm_suspend(struct drm_device *dev)
 
 	/* We do a lot of poking in a lot of registers, make sure they work
 	 * properly. */
-	intel_display_set_init_power(dev_priv, true);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_display_set_init_power(dev_priv, true);
+	else
+		intel_runtime_pm_get(dev_priv);
+
 	if (INTEL_INFO(dev_priv)->num_pipes)
 		drm_kms_helper_poll_disable(dev);
 
@@ -1670,7 +1690,10 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 
 	i915_gem_suspend_late(dev_priv);
 
-	intel_display_set_init_power(dev_priv, false);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_display_set_init_power(dev_priv, false);
+	else
+		intel_runtime_pm_put(dev_priv);
 	intel_uncore_suspend(dev_priv);
 
 	/*
@@ -1900,8 +1923,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	if (dev_priv->power_domains_suspended)
 		intel_power_domains_init_hw(dev_priv, true);
-	else
-		intel_display_set_init_power(dev_priv, true);
+	else {
+		if (INTEL_INFO(dev_priv)->num_pipes)
+			intel_display_set_init_power(dev_priv, true);
+		else
+			intel_runtime_pm_get(dev_priv);
+	}
 
 	intel_engines_sanitize(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 19ecd5787946..f8e73fba647a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -796,6 +796,9 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -2926,9 +2929,13 @@ void intel_power_domains_fini(struct drm_i915_private *dev_priv)
 	 * intel_runtime_pm_enable(). We have to hand back the control of the
 	 * device to the core with this reference held.
 	 */
-	intel_display_set_init_power(dev_priv, true);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_display_set_init_power(dev_priv, true);
+	else
+		intel_runtime_pm_get(dev_priv);
 
 	/* Remove the refcount we took to keep power well support disabled. */
+	// TODO understand and handle disabe_power_well
 	if (!i915_modparams.disable_power_well)
 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
@@ -3110,6 +3117,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 	struct i915_power_well *well;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
 	if (!INTEL_INFO(dev_priv)->num_pipes)
 		return;
 
@@ -3179,7 +3187,7 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	if (!INTEL_INFO(dev_priv)->num_pipes)
-		goto skip_dbuf_cdclk;
+		return;
 
 	gen9_dbuf_disable(dev_priv);
 
@@ -3187,7 +3195,6 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	/* The spec doesn't call for removing the reset handshake flag */
 
-skip_dbuf_cdclk:
 	/*
 	 * Disable PW1 (PG1).
 	 * Note that even though the driver's request is removed power well 1
-- 
2.18.0