[PATCH 5/7] wa

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem.c          |  4 ----
 drivers/gpu/drm/i915/intel_workarounds.c | 28 +++++++++++++++++++++++-
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 93efd92362db..4eb42ec1ecf4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5231,10 +5231,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
-	if (IS_HASWELL(dev_priv))
-		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
-			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
-
 	if (HAS_PCH_NOP(dev_priv)) {
 		if (IS_IVYBRIDGE(dev_priv)) {
 			u32 temp = I915_READ(GEN7_MSG_CTL);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..49ace5ced4eb 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -554,6 +554,30 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
 	return 0;
 }
 
+static void hsw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	I915_WRITE(MI_PREDICATE_RESULT_2,
+		   INTEL_INFO(dev_priv)->gt == 3 ?
+		   LOWER_SLICE_ENABLED :
+		   LOWER_SLICE_DISABLED);
+
+#define RING_WAIT_FOR_RC6_EXIT(base)   _MMIO((base) + 0xcc)
+#define   RING_RC6_SEL_WRITE_ADDR_MASK         (0x7 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_MULTICAST    (0x0 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_UPPER_LEFT   (0x4 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_UPPER_RIGHT  (0x5 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_LOWER_LEFT   (0x6 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_LOWER_RIGHT  (0x7 << 4)
+
+	for_each_engine(engine, dev_priv, id)
+		I915_WRITE(RING_WAIT_FOR_RC6_EXIT(engine->mmio_base),
+			   _MASKED_FIELD(RING_RC6_SEL_WRITE_ADDR_MASK,
+					 RING_RC6_SEL_WRITE_ADDR_UPPER_LEFT));
+}
+
 static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
 }
@@ -883,8 +907,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) < 8)
+	if (INTEL_GEN(dev_priv) < 7 || !IS_HASWELL(dev_priv))
 		return;
+	else if (IS_HASWELL(dev_priv))
+		hsw_gt_workarounds_apply(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		bdw_gt_workarounds_apply(dev_priv);
 	else if (IS_CHERRYVIEW(dev_priv))
-- 
2.17.1