[PATCH 9/9] wa

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem.c          |  4 --
 drivers/gpu/drm/i915/intel_ringbuffer.c  | 49 ++----------------------
 drivers/gpu/drm/i915/intel_workarounds.c | 30 ++++++++++++++-
 3 files changed, 32 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8dd4d35655af..7ce5eabc0f27 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5231,10 +5231,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
-	if (IS_HASWELL(dev_priv))
-		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
-			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
-
 	if (HAS_PCH_NOP(dev_priv)) {
 		if (IS_IVYBRIDGE(dev_priv)) {
 			u32 temp = I915_READ(GEN7_MSG_CTL);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ef3c76425843..90271d4d54a6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1518,12 +1518,6 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
 {
 	struct drm_i915_private *i915 = rq->i915;
 	struct intel_engine_cs *engine = rq->engine;
-	enum intel_engine_id id;
-	const int num_rings =
-		/* Use an extended w/a on gen7 if signalling from other rings */
-		(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
-		INTEL_INFO(i915)->num_rings - 1 :
-		0;
 	bool force_restore = false;
 	int len;
 	u32 *cs;
@@ -1537,7 +1531,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
 
 	len = 4;
 	if (IS_GEN7(i915))
-		len += 2 + (num_rings ? 4*num_rings + 6 : 0);
+		len += 2;
 	if (flags & MI_FORCE_RESTORE) {
 		GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
 		flags &= ~MI_FORCE_RESTORE;
@@ -1550,23 +1544,8 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
 		return PTR_ERR(cs);
 
 	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
-	if (IS_GEN7(i915)) {
+	if (IS_GEN7(i915))
 		*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
-		if (num_rings) {
-			struct intel_engine_cs *signaller;
-
-			*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-			for_each_engine(signaller, i915, id) {
-				if (signaller == engine)
-					continue;
-
-				*cs++ = i915_mmio_reg_offset(
-					   RING_PSMI_CTL(signaller->mmio_base));
-				*cs++ = _MASKED_BIT_ENABLE(
-						GEN6_PSMI_SLEEP_MSG_DISABLE);
-			}
-		}
-	}
 
 	if (force_restore) {
 		/*
@@ -1597,30 +1576,8 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
 	 */
 	*cs++ = MI_NOOP;
 
-	if (IS_GEN7(i915)) {
-		if (num_rings) {
-			struct intel_engine_cs *signaller;
-			i915_reg_t last_reg = {}; /* keep gcc quiet */
-
-			*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
-			for_each_engine(signaller, i915, id) {
-				if (signaller == engine)
-					continue;
-
-				last_reg = RING_PSMI_CTL(signaller->mmio_base);
-				*cs++ = i915_mmio_reg_offset(last_reg);
-				*cs++ = _MASKED_BIT_DISABLE(
-						GEN6_PSMI_SLEEP_MSG_DISABLE);
-			}
-
-			/* Insert a delay before the next switch! */
-			*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
-			*cs++ = i915_mmio_reg_offset(last_reg);
-			*cs++ = i915_ggtt_offset(engine->scratch);
-			*cs++ = MI_NOOP;
-		}
+	if (IS_GEN7(i915))
 		*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
-	}
 
 	intel_ring_advance(rq, cs);
 
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..31eb7c35df5f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -554,6 +554,32 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
 	return 0;
 }
 
+static void hsw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	I915_WRITE(MI_PREDICATE_RESULT_2,
+		   INTEL_INFO(dev_priv)->gt == 3 ?
+		   LOWER_SLICE_ENABLED :
+		   LOWER_SLICE_DISABLED);
+
+#define RING_WAIT_FOR_RC6_EXIT(base)   _MMIO((base) + 0xcc)
+#define   RING_RC6_SEL_WRITE_ADDR_MASK         (0x7 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_MULTICAST    (0x0 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_UPPER_LEFT   (0x4 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_UPPER_RIGHT  (0x5 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_LOWER_LEFT   (0x6 << 4)
+#define   RING_RC6_SEL_WRITE_ADDR_LOWER_RIGHT  (0x7 << 4)
+
+	if (INTEL_INFO(dev_priv)->gt == 1) {
+		for_each_engine(engine, dev_priv, id)
+			I915_WRITE(RING_WAIT_FOR_RC6_EXIT(engine->mmio_base),
+				   _MASKED_FIELD(RING_RC6_SEL_WRITE_ADDR_MASK,
+						 RING_RC6_SEL_WRITE_ADDR_UPPER_LEFT));
+	}
+}
+
 static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
 }
@@ -883,8 +909,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) < 8)
+	if (INTEL_GEN(dev_priv) < 7 || !IS_HASWELL(dev_priv))
 		return;
+	else if (IS_HASWELL(dev_priv))
+		hsw_gt_workarounds_apply(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		bdw_gt_workarounds_apply(dev_priv);
 	else if (IS_CHERRYVIEW(dev_priv))
-- 
2.17.1