✓ Fi.CI.BAT: success for series starting with [01/38] drm/i915/gtt: Add read only pages to gen8_pte_encode

[Patchwork]

== Series Details ==

Series: series starting with [01/38] drm/i915/gtt: Add read only pages to gen8_pte_encode
URL   : https://patchwork.freedesktop.org/series/45679/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4409 -> Trybot_2454 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/45679/revisions/1/mbox/


== Changes ==

  No changes found


== Participating hosts (45 -> 40) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4409 -> Trybot_2454

  CI_DRM_4409: bf99024d9c80d81968d3621ead0c0c05343fe826 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4532: 840d12e2f050b784552197403d6575a57b6e896d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Trybot_2454: 34612dd182d83ba25ea32db1484b01625ed6d6e5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

34612dd182d8 drm/i915: Remove GPU reset dependence on struct_mutex
8d7158a7d7cb drm/i915: Pull all the reset functionality together into i915_reset.c
a1ded5ef8185 drm/i915: Dynamically allocate the array of drm_i915_gem_fence_reg
f5272b7fa5c2 drm/i915: Move fence-reg interface to i915_gem_fence_reg.h
bc3de76b3a95 drm/i915: Tidy i915_gem_suspend()
d11936e7fffe drm/i915: Convert fences to use a GGTT lock rather than struct_mutex
00c2d94a7fef drm/i915: Move fence register tracking to GGTT
c187659f4bc1 drm/i915: Introduce i915_address_space.mutex
105097bbf83a drm/i915: Stop tracking MRU activity on VMA
8b1d9ffdde56 RFC drm/i915: Load balancing across a virtual engine
b8207afe4565 drm/i915: Replace nested subclassing with explicit subclasses
874deed5d9ce drm/i915/execlists: Refactor out can_merge_rq()
3b2a65ec6545 drm/i915/execlists: Flush the tasklet before unpinning
589f3a459c5c drm/i915: Allow a context to define its set of engines
6bba90ea0eb6 drm/i915: Re-arrange execbuf so context is known before engine
d7c70ad6ece7 drm/i915: Fix I915_EXEC_RING_MASK
b2d7a4740197 drm/i915: Allow contexts to share a single timeline across all engines
7981dcf92d07 drm/i915: Extend CREATE_CONTEXT to allow inheritance ala clone()
69a186a997a8 drm/i915: Introduce the i915_user_extension_method
1e1bd18804fc drm/i915: Track the last-active inside the i915_vma
3808110908b6 drm/i915: Track vma activity per fence.context, not per engine
cd7c2cca978d drm/i915: Move i915_vma_move_to_active() to i915_vma.c
e8a180e47666 drm/i915: Start returning an error from i915_vma_move_to_active()
35570ba532b6 drm/i915: Export i915_request_skip()
3fb64fceeff5 drm/i915: Refactor export_fence() after i915_vma_move_to_active()
9389252dc46a drm/i915: Priority boost switching to an idle ring
8f96ec99fead drm/i915: Priority boost for new clients
60afd0a4ce31 drm/i915: Combine multiple internal plists into the same i915_priolist bucket
3b89bb8eaba6 drm/i915: Reserve some priority bits for internal use
04324bcf1c94 drm/i915/execlists: Switch to rb_root_cached
8e5604367118 drm/i915: Hold request reference for submission until retirement
7ef9d29f4a12 drm/i915: Move engine request retirement to intel_engine_cs
898232be3f57 drm/i915: Move rate-limiting request retire to after submission
182d52ff07c8 drm/i915/userptr: Enable read-only support on gen8+
b210b0c7f6f7 drm/i915: Reject attempted pwrites into a read-only object
399d9afbff24 drm/i915: Prevent writing into a read-only object via a GGTT mmap
b966c58e3763 drm/i915/gtt: Read-only pages for insert_entries on bdw+
419445b6a675 drm/i915/gtt: Add read only pages to gen8_pte_encode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2454/issues.html