[PATCH 2/4] drm/i915/guc: Use GuC BO API for firmware DMA
Jackie Li
yaodong.li at intel.com
Fri Mar 2 22:09:43 UTC 2018
Current fw upload code pins the FW GEM buffer in uc_fw layer which voilates
the layer isolation since it needs to access GUC_WOPCM_TOP to make sure
the buffer is pinned to correct GGTT offset. Furthermore, for the GuC DMA
engine setup, current code uses duplicated code structure to setup the GuC
DMA hardware which is unnecessary and also problemetic - e.g. current code
tries to copy RSA to Scratch regs with GEM object pinned into GGTT which
is unnecessary since GuC FW is not even up and running yet.
This patch firstly introduces a more generic function to do the DMA using
GuC DMA engine. Furthermore, this function continues to reuse GuC BO API to
enforce the GuC GGTT offset restriction while pinning a GEM buffer to GGTT.
so that we can simplifies the funcitionality as "Transfer a GEM object to
WOPCM (current only supports WOPCM as the destination) with GuC DMA"
and all GuC buffer pinning/unpinning operations + DMA engine setup are
all encapsulputed in this signal function. This patch also updates the UC
FW uploading code to switch to this new function.
Signed-off-by: Jackie Li <yaodong.li at intel.com>
---
drivers/gpu/drm/i915/intel_guc.c | 75 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_guc.h | 2 +
drivers/gpu/drm/i915/intel_guc_bo.c | 84 +++++++++++++++++++++----------
drivers/gpu/drm/i915/intel_guc_bo.h | 4 ++
drivers/gpu/drm/i915/intel_guc_fw.c | 99 ++++++++++++++-----------------------
drivers/gpu/drm/i915/intel_huc_fw.c | 50 ++++++-------------
drivers/gpu/drm/i915/intel_uc_fw.c | 30 +----------
drivers/gpu/drm/i915/intel_uc_fw.h | 3 +-
8 files changed, 195 insertions(+), 152 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 151bba1..8ec3f49 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -469,3 +469,78 @@ u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
return wopcm_size;
}
+
+#define GUC_DMA_FLAGS_MASK (HUC_UKERNEL | UOS_MOVE)
+
+/**
+ * intel_guc_dma_xfer() - DMA a GEM buffer into WOPCM.
+ * @guc: intel_guc structure.
+ * @obj: i915 GEM buffer object.
+ * @src: offset in @obj were DMA source starts.
+ * @dst: offset in WOPCM were DMA destination starts.
+ * @dma_flags: flags that pass to DMA_CTRL register.
+ *
+ * This functions initiates a data transfer from given GEM buffer @obj to WOPCM
+ * by using GuC DMA engine.
+ *
+ * Return: 0 on success. Error code will be returned on failure.
+ */
+int intel_guc_dma_xfer(struct intel_guc *guc, struct drm_i915_gem_object *obj,
+ u64 src, u64 dst, u32 size, u32 dma_flags)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ u32 dst_lo = lower_32_bits(dst);
+ u32 dst_hi = upper_32_bits(dst);
+ struct intel_guc_bo *guc_bo;
+ u32 status = 0;
+ int err;
+
+ DRM_DEBUG_DRIVER("DMA from %llu to %llu, size %u, flags %#x\n", src,
+ dst, size, dma_flags);
+
+ /* Make sure all control bits are cleared before starting a new DMA. */
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(GUC_DMA_FLAGS_MASK));
+
+ /* In case any CPU access is still on-going after DMA is started. */
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err) {
+ DRM_ERROR("Failed move buffer to GTT domain. err =%d\n", err);
+ return err;
+ }
+
+ /* GGTT mapping needs to be setup for GuC DMA engine. */
+ guc_bo = intel_guc_bo_alloc_from_gem_obj(guc, obj, false);
+ if (IS_ERR(guc_bo)) {
+ DRM_ERROR("Failed to wrap GEM object to GuC BO.\n");
+ return PTR_ERR(guc_bo);
+ }
+
+ /*
+ * Buffer is ready to use, Now configure DMA engine.
+ */
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ I915_WRITE(DMA_COPY_SIZE, size);
+
+ src += guc_bo->ggtt_offset;
+ I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(src));
+ I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(src) & 0xffff);
+
+ I915_WRITE(DMA_ADDR_1_LOW, dst_lo);
+ I915_WRITE(DMA_ADDR_1_HIGH, dst_hi | DMA_ADDRESS_SPACE_WOPCM);
+
+ dma_flags &= GUC_DMA_FLAGS_MASK;
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(dma_flags | START_DMA));
+
+ err = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
+ 2, 100, &status);
+
+ DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ /* DMA was complete. OK to free GuC BO. */
+ intel_guc_bo_free(guc_bo);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index adf03b7..ed8300c 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -129,5 +129,7 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
int intel_guc_suspend(struct drm_i915_private *dev_priv);
int intel_guc_resume(struct drm_i915_private *dev_priv);
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
+int intel_guc_dma_xfer(struct intel_guc *guc, struct drm_i915_gem_object *obj,
+ u64 src, u64 dst, u32 size, u32 dma_flags);
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_bo.c b/drivers/gpu/drm/i915/intel_guc_bo.c
index e7bd5c7..ee5d793 100644
--- a/drivers/gpu/drm/i915/intel_guc_bo.c
+++ b/drivers/gpu/drm/i915/intel_guc_bo.c
@@ -8,26 +8,11 @@
#include "intel_guc.h"
#include "i915_drv.h"
-/**
- * intel_guc_bo_alloc() - Allocate an intel_guc_bo object.
- * @guc: intel_guc structure.
- * @size: size in byte of the GuC buffer object.
- * @cpu_map: whether pin and map this GuC buffer object in CPU address space.
- *
- * GuC hardware requires an i915 GEM object to be pinned above GUC_WOPCM_TOP.
- * This function serves as a wrapper to allocate, pin a i915 GEM object in to
- * both GGTT and CPU address space by enforcing the GuC hardware requirement
- * on the GGTT offset bias while pinning the buffer to GGTT address space.
- * Depends on the @cpu_map flags, this function will pin and map the GEM object
- * into CPU address space with I915_MAP_WB cache policy if @cpu_map was true.
- *
- * Return: An intel_guc_bo on success. ERR_PTR will be returned on failure.
- */
-struct intel_guc_bo *intel_guc_bo_alloc(struct intel_guc *guc, u32 size,
- bool cpu_map)
+static struct intel_guc_bo *intel_guc_bo_create(struct intel_guc *guc,
+ struct drm_i915_gem_object *obj,
+ bool cpu_map)
{
struct drm_i915_private *i915 = guc_to_i915(guc);
- struct drm_i915_gem_object *obj;
struct intel_guc_bo *guc_bo;
void *err_ptr;
int err;
@@ -36,12 +21,6 @@ struct intel_guc_bo *intel_guc_bo_alloc(struct intel_guc *guc, u32 size,
if (!guc_bo)
return ERR_PTR(-ENOMEM);
- obj = i915_gem_object_create(i915, size);
- if (IS_ERR(obj)) {
- err_ptr = ERR_CAST(obj);
- goto obj_err;
- }
-
guc_bo->vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
if (IS_ERR(guc_bo->vma)) {
err_ptr = ERR_CAST(guc_bo->vma);
@@ -72,13 +51,66 @@ struct intel_guc_bo *intel_guc_bo_alloc(struct intel_guc *guc, u32 size,
pin_err:
i915_vma_close(guc_bo->vma);
vma_err:
- i915_gem_object_put(obj);
-obj_err:
kfree(guc_bo);
return err_ptr;
}
/**
+ * intel_guc_bo_alloc() - Allocate an intel_guc_bo object.
+ * @guc: intel_guc structure.
+ * @size: size in byte of the GuC buffer object.
+ * @cpu_map: whether pin and map this GuC buffer object in CPU address space.
+ *
+ * GuC hardware requires an i915 GEM object to be pinned above GUC_WOPCM_TOP.
+ * This function serves as a wrapper to allocate, pin a i915 GEM object in to
+ * both GGTT and CPU address space by enforcing the GuC hardware requirement
+ * on the GGTT offset bias while pinning the buffer to GGTT address space.
+ * Depends on the @cpu_map flags, this function will pin and map the GEM object
+ * into CPU address space with I915_MAP_WB cache policy if @cpu_map was true.
+ *
+ * Return: An intel_guc_bo on success. ERR_PTR will be returned on failure.
+ */
+struct intel_guc_bo *intel_guc_bo_alloc(struct intel_guc *guc, u32 size,
+ bool cpu_map)
+{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_object_create(i915, size);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ return intel_guc_bo_create(guc, obj, cpu_map);
+}
+
+/**
+ * intel_guc_bo_alloc_from_gem_obj() - Wrap an external GEM buffer into GuC BO.
+ * @guc: intel_guc structure.
+ * @obj: i915 GEM buffer object.
+ * @cpu_map: whether pin and map this GuC buffer object in CPU address space.
+ *
+ * This function pin an external @obj into GGTT address space above
+ * GGUC_WOPCM_TOP. It will also pin and map the @obj into CPU address space if
+ * @cpu_map is true.
+ *
+ * Return: An intel_guc_bo on success. ERR_PTR will be returned on failure.
+ */
+struct intel_guc_bo *
+intel_guc_bo_alloc_from_gem_obj(struct intel_guc *guc,
+ struct drm_i915_gem_object *obj,
+ bool cpu_map)
+{
+ /*
+ * Get a reference of this external GEM object, so that we can free
+ * the GuC BO with intel_guc_bo_free() without worrying about the
+ * call to i915_gem_object_put().
+ */
+ i915_gem_object_get(obj);
+
+ return intel_guc_bo_create(guc, obj, cpu_map);
+}
+
+/**
* intel_guc_bo_free() - Free an GuC buffer object.
* @guc_bo: intel_guc_bo needs to be freed.
*
diff --git a/drivers/gpu/drm/i915/intel_guc_bo.h b/drivers/gpu/drm/i915/intel_guc_bo.h
index 547d201..7b98432 100644
--- a/drivers/gpu/drm/i915/intel_guc_bo.h
+++ b/drivers/gpu/drm/i915/intel_guc_bo.h
@@ -29,6 +29,10 @@ struct intel_guc_bo {
struct intel_guc_bo *intel_guc_bo_alloc(struct intel_guc *guc, u32 size,
bool cpu_map);
+struct intel_guc_bo *
+intel_guc_bo_alloc_from_gem_obj(struct intel_guc *guc,
+ struct drm_i915_gem_object *obj,
+ bool cpu_map);
void intel_guc_bo_free(struct intel_guc_bo *guc_bo);
#endif /* _INTEL_GUC_BO_H_ */
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index d07f2b9..4672ff9 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -125,14 +125,23 @@ static void guc_prepare_xfer(struct intel_guc *guc)
}
/* Copy RSA signature from the fw image to HW for verification */
-static int guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma)
+static int guc_xfer_rsa(struct intel_guc *guc, struct drm_i915_gem_object *obj)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_uc_fw *guc_fw = &guc->fw;
- struct sg_table *sg = vma->pages;
u32 rsa[UOS_RSA_SCRATCH_COUNT];
+ struct sg_table *sg;
+ int err;
int i;
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ if (unlikely(i915_gem_object_set_to_cpu_domain(obj, true)))
+ goto out;
+
+ sg = obj->mm.pages;
if (sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa),
guc_fw->rsa_offset) != sizeof(rsa))
return -EINVAL;
@@ -140,51 +149,9 @@ static int guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma)
for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
- return 0;
-}
-
-/*
- * Transfer the firmware image to RAM for execution by the microcontroller.
- *
- * Architecturally, the DMA engine is bidirectional, and can potentially even
- * transfer between GTT locations. This functionality is left out of the API
- * for now as there is no need for it.
- */
-static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct intel_uc_fw *guc_fw = &guc->fw;
- unsigned long offset;
- u32 status;
- int ret;
-
- /*
- * The header plus uCode will be copied to WOPCM via DMA, excluding any
- * other components
- */
- I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
-
- /* Set the source address for the new blob */
- offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
- I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
- I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
-
- /*
- * Set the DMA destination. Current uCode expects the code to be
- * loaded at 8k; locations below this are used for the stack.
- */
- I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
- I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
-
- /* Finally start the DMA */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
-
- /* Wait for DMA to finish */
- ret = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
- 2, 100, &status);
- DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);
-
- return ret;
+out:
+ i915_gem_object_unpin_pages(obj);
+ return err;
}
/*
@@ -232,17 +199,24 @@ static int guc_wait_ucode(struct intel_guc *guc)
}
/*
+ * Set the DMA destination. Current uCode expects the code to be
+ * loaded at 8KiB; locations below this are used for the stack.
+ */
+#define GUC_FW_DST_OFFSET (8 * 1024)
+
+/*
* Load the GuC firmware blob into the MinuteIA.
*/
-static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
+static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- int ret;
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+ u32 guc_fw_size = guc->fw.header_size + guc->fw.ucode_size;
+ int err;
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
guc_prepare_xfer(guc);
@@ -251,21 +225,22 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
* by the DMA engine in one operation, whereas the RSA signature is
* loaded via MMIO.
*/
- ret = guc_xfer_rsa(guc, vma);
- if (ret)
- DRM_WARN("GuC firmware signature xfer error %d\n", ret);
+ err = guc_xfer_rsa(guc, guc->fw.obj);
+ if (err)
+ DRM_WARN("GuC firmware signature xfer error %d\n", err);
- ret = guc_xfer_ucode(guc, vma);
- if (ret)
- DRM_WARN("GuC firmware code xfer error %d\n", ret);
+ err = intel_guc_dma_xfer(guc, guc_fw->obj, guc_fw->header_offset,
+ GUC_FW_DST_OFFSET, guc_fw_size, UOS_MOVE);
+ if (err)
+ DRM_WARN("GuC firmware code xfer error %d\n", err);
- ret = guc_wait_ucode(guc);
- if (ret)
- DRM_ERROR("GuC firmware xfer error %d\n", ret);
+ err = guc_wait_ucode(guc);
+ if (err)
+ DRM_ERROR("GuC firmware xfer error %d\n", err);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(i915, FORCEWAKE_ALL);
- return ret;
+ return err;
}
/**
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
index c66afa9..292bb1a 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -99,52 +99,34 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
/**
* huc_fw_xfer() - DMA's the firmware
* @huc_fw: the firmware descriptor
- * @vma: the firmware image (bound into the GGTT)
*
- * Transfer the firmware image to RAM for execution by the microcontroller.
+ * Transfer the firmware image to WOPCM for execution by the microcontroller.
+ * Currently, GuC DMA is used for transferring the firmware.
*
* Return: 0 on success, non-zero on failure
*/
-static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
+static int huc_fw_xfer(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
- struct drm_i915_private *dev_priv = huc_to_i915(huc);
- unsigned long offset = 0;
- u32 size;
- int ret;
+ struct drm_i915_private *i915 = huc_to_i915(huc);
+ u32 huc_fw_size = huc->fw.header_size + huc->fw.ucode_size;
+ struct intel_guc *guc = &i915->guc;
+ int err;
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
-
- /* Set the source address for the uCode */
- offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
- I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
- I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
-
- /* Hardware doesn't look at destination address for HuC. Set it to 0,
+ /*
+ * Hardware doesn't look at destination address for HuC. Set it to 0,
* but still program the correct address space.
*/
- I915_WRITE(DMA_ADDR_1_LOW, 0);
- I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
-
- size = huc_fw->header_size + huc_fw->ucode_size;
- I915_WRITE(DMA_COPY_SIZE, size);
-
- /* Start the DMA */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
-
- /* Wait for DMA to finish */
- ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
-
- DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
-
- /* Disable the bits once DMA is over */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
-
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ err = intel_guc_dma_xfer(guc, huc_fw->obj, huc_fw->header_offset,
+ 0, huc_fw_size, HUC_UKERNEL);
+ if (err) {
+ DRM_ERROR("Failed to DMA HuC FW. err = %d\n", err);
+ return err;
+ }
- return ret;
+ return 0;
}
/**
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 3ec0ce5..b98e74f 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -205,10 +205,8 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
* Return: 0 on success, non-zero on failure.
*/
int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
- int (*xfer)(struct intel_uc_fw *uc_fw,
- struct i915_vma *vma))
+ int (*xfer)(struct intel_uc_fw *uc_fw))
{
- struct i915_vma *vma;
int err;
DRM_DEBUG_DRIVER("%s fw load %s\n",
@@ -222,32 +220,8 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
intel_uc_fw_type_repr(uc_fw->type),
intel_uc_fw_status_repr(uc_fw->load_status));
- /* Pin object with firmware */
- err = i915_gem_object_set_to_gtt_domain(uc_fw->obj, false);
- if (err) {
- DRM_DEBUG_DRIVER("%s fw set-domain err=%d\n",
- intel_uc_fw_type_repr(uc_fw->type), err);
- goto fail;
- }
-
- vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
- PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
- if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
- intel_uc_fw_type_repr(uc_fw->type), err);
- goto fail;
- }
-
/* Call custom loader */
- err = xfer(uc_fw, vma);
-
- /*
- * We keep the object pages for reuse during resume. But we can unpin it
- * now that DMA has completed, so it doesn't continue to take up space.
- */
- i915_vma_unpin(vma);
-
+ err = xfer(uc_fw);
if (err)
goto fail;
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..4e5431e 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -118,8 +118,7 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
struct intel_uc_fw *uc_fw);
int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
- int (*xfer)(struct intel_uc_fw *uc_fw,
- struct i915_vma *vma));
+ int (*xfer)(struct intel_uc_fw *uc_fw));
void intel_uc_fw_fini(struct intel_uc_fw *uc_fw);
void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p);
--
2.7.4
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