[PATCH 3/4] drm/i915/guc: Extend GuC BO to HuC FW authentication

[Jackie Li]

HuC needs to pin the FW Gem object to valid GuC GGTT space which is relies
on pinning VMA to GGTT with GUC_WOPCM_TOP.

Since we've already had a central place to enforce these rules, this patch
update the HuC authentication code to use GuC BO APIs.

Signed-off-by: Jackie Li <yaodong.li at intel.com>
---
 drivers/gpu/drm/i915/intel_huc.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index e37f58e..d2ba658 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -47,22 +47,20 @@ int intel_huc_auth(struct intel_huc *huc)
 {
 	struct drm_i915_private *i915 = huc_to_i915(huc);
 	struct intel_guc *guc = &i915->guc;
-	struct i915_vma *vma;
+	struct intel_guc_bo *guc_bo;
 	int ret;
 
 	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 		return -ENOEXEC;
 
-	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
-				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
-	if (IS_ERR(vma)) {
-		ret = PTR_ERR(vma);
+	guc_bo = intel_guc_bo_alloc_from_gem_obj(guc, huc->fw.obj, false);
+	if (IS_ERR(guc_bo)) {
+		ret = PTR_ERR(guc_bo);
 		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
 		return ret;
 	}
 
-	ret = intel_guc_auth_huc(guc,
-				 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
+	ret = intel_guc_auth_huc(guc, guc_bo->ggtt_offset + huc->fw.rsa_offset);
 	if (ret) {
 		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
 		goto out;
@@ -80,6 +78,6 @@ int intel_huc_auth(struct intel_huc *huc)
 	}
 
 out:
-	i915_vma_unpin(vma);
+	intel_guc_bo_free(guc_bo);
 	return ret;
 }
-- 
2.7.4