[PATCH 24/24] drm/i915: Split control of rps and rc6
Chris Wilson
chris at chris-wilson.co.uk
Sat Mar 10 10:11:49 UTC 2018
Allow ourselves to individually toggle rps or rc6.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.c | 6 +--
drivers/gpu/drm/i915/i915_drv.h | 5 ---
drivers/gpu/drm/i915/i915_gem.c | 23 +++++------
drivers/gpu/drm/i915/i915_request.c | 4 +-
drivers/gpu/drm/i915/intel_display.c | 5 ++-
drivers/gpu/drm/i915/intel_gt_pm.c | 75 +++++++++++++++---------------------
drivers/gpu/drm/i915/intel_gt_pm.h | 14 ++++---
7 files changed, 60 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 127bd2a6e9cb..7bc73cdfe39d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1063,7 +1063,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
*/
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
- intel_sanitize_gt_powersave(dev_priv);
+ intel_gt_pm_sanitize(dev_priv);
intel_uncore_fini(dev_priv);
i915_mmio_cleanup(dev_priv);
pci_dev_put(dev_priv->bridge_dev);
@@ -1172,7 +1172,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
intel_uncore_sanitize(dev_priv);
/* BIOS often leaves RC6 enabled, but disable it for hw init */
- intel_sanitize_gt_powersave(dev_priv);
+ intel_gt_pm_sanitize(dev_priv);
intel_opregion_setup(dev_priv);
@@ -1715,7 +1715,7 @@ static int i915_drm_resume(struct drm_device *dev)
int ret;
disable_rpm_wakeref_asserts(dev_priv);
- intel_sanitize_gt_powersave(dev_priv);
+ intel_gt_pm_sanitize(dev_priv);
ret = i915_ggtt_enable_hw(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 282f585e5b8d..e9ae0a62e8a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -784,14 +784,9 @@ struct intel_rc6 {
u64 cur_residency[4];
};
-struct intel_llc_pstate {
- bool enabled;
-};
-
struct intel_gen6_power_mgmt {
struct intel_rps rps;
struct intel_rc6 rc6;
- struct intel_llc_pstate llc_pstate;
};
/* defined intel_pm.c */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8c8b8cbe6b90..9b0cf7d175cd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3165,8 +3165,9 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
i915_gem_restore_fences(dev_priv);
if (dev_priv->gt.awake) {
- intel_sanitize_gt_powersave(dev_priv);
- intel_enable_gt_powersave(dev_priv);
+ intel_gt_pm_sanitize(dev_priv);
+ intel_gt_pm_enable_rps(dev_priv);
+ intel_gt_pm_enable_rc6(dev_priv);
if (INTEL_GEN(dev_priv) >= 6)
gen6_rps_busy(dev_priv);
}
@@ -5314,10 +5315,12 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto err_unlock;
}
+ intel_gt_pm_init(dev_priv);
+
ret = i915_gem_contexts_init(dev_priv);
if (ret) {
GEM_BUG_ON(ret == -EIO);
- goto err_ggtt;
+ goto err_pm;
}
ret = intel_engines_init(dev_priv);
@@ -5326,11 +5329,9 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto err_context;
}
- intel_init_gt_powersave(dev_priv);
-
ret = intel_uc_init(dev_priv);
if (ret)
- goto err_pm;
+ goto err_engines;
ret = i915_gem_init_hw(dev_priv);
if (ret)
@@ -5378,15 +5379,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uc_fini_hw(dev_priv);
err_uc_init:
intel_uc_fini(dev_priv);
-err_pm:
- if (ret != -EIO) {
- intel_cleanup_gt_powersave(dev_priv);
+err_engines:
+ if (ret != -EIO)
i915_gem_cleanup_engines(dev_priv);
- }
err_context:
if (ret != -EIO)
i915_gem_contexts_fini(dev_priv);
-err_ggtt:
+err_pm:
+ if (ret != -EIO)
+ intel_gt_pm_fini(dev_priv);
err_unlock:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 3605d5f1a226..624c7cd207d2 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -274,7 +274,9 @@ static void mark_busy(struct drm_i915_private *i915)
if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
i915->gt.epoch = 1;
- intel_enable_gt_powersave(i915);
+ intel_gt_pm_enable_rps(i915);
+ intel_gt_pm_enable_rc6(i915);
+
i915_update_gfx_val(i915);
if (INTEL_GEN(i915) >= 6)
gen6_rps_busy(i915);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0f20573930f4..e13e47fdf284 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15421,7 +15421,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
flush_work(&dev_priv->atomic_helper.free_work);
WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
- intel_disable_gt_powersave(dev_priv);
+ intel_gt_pm_disable_rps(dev_priv);
+ intel_gt_pm_disable_rc6(dev_priv);
/*
* Interrupts and polling as the first thing to avoid creating havoc.
@@ -15450,7 +15451,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
intel_cleanup_overlay(dev_priv);
- intel_cleanup_gt_powersave(dev_priv);
+ intel_gt_pm_fini(dev_priv);
intel_teardown_gmbus(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index 8281494c53d5..d9cb55b18354 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -2219,11 +2219,13 @@ static void intel_init_emon(struct drm_i915_private *dev_priv)
dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
}
-void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_sanitize(struct drm_i915_private *dev_priv)
{
dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
+ intel_gt_pm_disable_rps(dev_priv);
+
dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
- intel_disable_gt_powersave(dev_priv);
+ intel_gt_pm_disable_rc6(dev_priv);
if (INTEL_GEN(dev_priv) < 11)
gen6_reset_rps_interrupts(dev_priv);
@@ -2231,7 +2233,7 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
WARN_ON_ONCE(1);
}
-void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_init(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -2287,22 +2289,13 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
/* Finally allow us to boost to max by default */
rps->boost_freq = rps->max_freq;
- mutex_unlock(&rps->lock);
-}
-
-static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
-{
- lockdep_assert_held(&i915->gt_pm.rps.lock);
-
- if (i915->gt_pm.llc_pstate.enabled)
- return;
+ if (INTEL_GEN(dev_priv) >= 6)
+ gen6_update_ring_freq(dev_priv);
- gen6_update_ring_freq(i915);
-
- i915->gt_pm.llc_pstate.enabled = true;
+ mutex_unlock(&rps->lock);
}
-static void intel_enable_rc6(struct drm_i915_private *dev_priv)
+static void __enable_rc6(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
@@ -2323,7 +2316,7 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
dev_priv->gt_pm.rc6.enabled = true;
}
-static void intel_enable_rps(struct drm_i915_private *dev_priv)
+static void __enable_rps(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -2358,37 +2351,27 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
rps->enabled = true;
}
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv)
{
- /* Powersaving is controlled by the host when inside a VM */
- if (intel_vgpu_active(dev_priv))
+ if (!HAS_RC6(dev_priv))
return;
mutex_lock(&dev_priv->gt_pm.rps.lock);
-
- if (HAS_RC6(dev_priv))
- intel_enable_rc6(dev_priv);
- if (HAS_RPS(dev_priv))
- intel_enable_rps(dev_priv);
- if (HAS_LLC(dev_priv))
- intel_enable_llc_pstate(dev_priv);
-
+ __enable_rc6(dev_priv);
mutex_unlock(&dev_priv->gt_pm.rps.lock);
}
-static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
+void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv)
{
- lockdep_assert_held(&i915->gt_pm.rps.lock);
-
- if (!i915->gt_pm.llc_pstate.enabled)
+ if (!HAS_RPS(dev_priv))
return;
- /* Currently there is no HW configuration to be done to disable. */
-
- i915->gt_pm.llc_pstate.enabled = false;
+ mutex_lock(&dev_priv->gt_pm.rps.lock);
+ __enable_rps(dev_priv);
+ mutex_unlock(&dev_priv->gt_pm.rps.lock);
}
-static void intel_disable_rc6(struct drm_i915_private *dev_priv)
+static void __disable_rc6(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
@@ -2407,7 +2390,14 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
dev_priv->gt_pm.rc6.enabled = false;
}
-static void intel_disable_rps(struct drm_i915_private *dev_priv)
+void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv)
+{
+ mutex_lock(&dev_priv->gt_pm.rps.lock);
+ __disable_rc6(dev_priv);
+ mutex_unlock(&dev_priv->gt_pm.rps.lock);
+}
+
+static void __disable_rps(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
@@ -2428,19 +2418,14 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
dev_priv->gt_pm.rps.enabled = false;
}
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv)
{
mutex_lock(&dev_priv->gt_pm.rps.lock);
-
- intel_disable_rc6(dev_priv);
- intel_disable_rps(dev_priv);
- if (HAS_LLC(dev_priv))
- intel_disable_llc_pstate(dev_priv);
-
+ __disable_rps(dev_priv);
mutex_unlock(&dev_priv->gt_pm.rps.lock);
}
-void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_fini(struct drm_i915_private *dev_priv)
{
if (IS_VALLEYVIEW(dev_priv))
valleyview_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
index d312bb994108..cb3e87304204 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -31,12 +31,16 @@ struct intel_rps_client;
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
-void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_gt_pm_sanitize(struct drm_i915_private *dev_priv);
-void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_gt_pm_init(struct drm_i915_private *dev_priv);
+void intel_gt_pm_fini(struct drm_i915_private *dev_priv);
+
+void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv);
+void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv);
+
+void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv);
+void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv);
void gen6_rps_busy(struct drm_i915_private *dev_priv);
void gen6_rps_idle(struct drm_i915_private *dev_priv);
--
2.16.2
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