[PATCH 3/4] drm/i915: check the CTL_STATE alone for PW#1

Ramalingam C ramalingam.c at intel.com
Fri Nov 2 16:49:23 UTC 2018


From: Imre Deak <imre.deak at intel.com>

on Gen 9, to check the state of the Power_well #1, we need to
check the CTL_STATE alone.

Signed-off-by: Imre Deak <imre.deak at intel.com>
Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f5416eb9644..727b6a4cdc85 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -478,6 +478,9 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 	u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
 		   HSW_PWR_WELL_CTL_STATE(pw_idx);
 
+	if (IS_GEN9(dev_priv) && power_well->desc->id == SKL_DISP_PW_1)
+		mask &= ~HSW_PWR_WELL_CTL_REQ(pw_idx);
+
 	return (I915_READ(regs->driver) & mask) == mask;
 }
 
-- 
2.7.4



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