[PATCH v5] Additional debug for watermarks

[Stanislav Lisovskiy]

Various kms_draw_crc tests fail with crc mismatch assertion.
Noticed that in almost all failure cases, there is no
skl_compute_wm call, while in those which pass, there is.
This issue seems to be extremely hard to reproduce
on a single machine(tried manually on kbl, skl, icl).
So added some traces and start tryboting to figure out
why skl_compute_wm call doesn't happen.

v3: Remove excessive messages, otherwise results in
    atomic update failure due to exceeding maximum time window.

v4: Print only if watermark/ddb values change.

v5: Remove prints and let watermarks be recalculated always.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c      | 20 ++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 31fbf67cb661..5187d6750d0f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12515,6 +12515,8 @@ static int intel_atomic_check(struct drm_device *dev,
 	if (ret)
 		return ret;
 
+	DRM_DEBUG_KMS("Validating state");
+
 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
 		struct intel_crtc_state *pipe_config =
 			to_intel_crtc_state(crtc_state);
@@ -12568,6 +12570,9 @@ static int intel_atomic_check(struct drm_device *dev,
 		return ret;
 
 	intel_fbc_choose_crtc(dev_priv, intel_state);
+
+	DRM_DEBUG_KMS("Calculating watermarks");
+
 	return calc_watermark_data(state);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9da8ff263d36..c1b0e5cd4c88 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5093,10 +5093,17 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
 				i915_reg_t reg,
 				const struct skl_ddb_entry *entry)
 {
+	static int last_start = -1, last_end = -1;
 	if (entry->end)
 		I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
 	else
 		I915_WRITE(reg, 0);
+
+	if ((last_start != entry->start) || (last_end != entry->end)) {
+		last_start = entry->start;
+		last_end = entry->end;
+	//	DRM_DEBUG_KMS("write ddb %d %d", last_start, last_end);
+	}
 }
 
 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
@@ -5104,6 +5111,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
 			       const struct skl_wm_level *level)
 {
 	uint32_t val = 0;
+	static int last_plane_res_b = -1, last_plane_res_l = -1;
 
 	if (level->plane_en) {
 		val |= PLANE_WM_EN;
@@ -5111,6 +5119,12 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
 		val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
 	}
 
+	if ((last_plane_res_b != level->plane_res_b) || (last_plane_res_l != level->plane_res_l)) {
+		last_plane_res_b = level->plane_res_b;
+		last_plane_res_l = level->plane_res_l;
+	//	DRM_DEBUG_KMS("write wm level %d %d", level->plane_res_b, level->plane_res_l);
+	}
+
 	I915_WRITE(reg, val);
 }
 
@@ -5220,6 +5234,10 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
 	else
 		*changed = true;
 
+	*changed = true;
+
+	//DRM_DEBUG_KMS("Pipe changed %d", *changed);
+
 	return 0;
 }
 
@@ -5452,6 +5470,8 @@ skl_compute_wm(struct drm_atomic_state *state)
 	if (ret)
 		return ret;
 
+//	DRM_DEBUG_KMS("calculating changes");
+
 	/*
 	 * Calculate WM's for all pipes that are part of this transaction.
 	 * Note that the DDB allocation above may have added more CRTC's that
-- 
2.17.1