[PATCH 08/14] drm/i915: Do not initialize display core when display is disabled

[José Roberto de Souza]

With display disabled, driver don't need to enable any power well
or load the DMC firmware.

The only thing that *_display_core_init will do when display is
disabled is call intel_pch_reset_handshake(), so PCH handshake
will be unset and in counterpart *_display_core_uninit() will
only disable DC.

The power wells enabled by BIOS during boot will be disabled in
futher patch.

Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 44 ++++++++++++++++++++++---
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8e0f361b9a4d..c795df21d851 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -593,6 +593,9 @@ void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 {
 	u32 val;
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 
 	DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
@@ -628,6 +631,9 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 	uint32_t val;
 	uint32_t mask;
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 		state &= dev_priv->csr.allowed_dc_mask;
 
@@ -833,11 +839,11 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 {
 	struct intel_cdclk_state cdclk_state = {};
 
-	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
 	dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -3344,6 +3350,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 	/* enable PCH reset handshake */
 	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	/* enable PG1 and Misc I/O */
 	mutex_lock(&power_domains->lock);
 
@@ -3368,6 +3377,9 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	gen9_dbuf_disable(dev_priv);
@@ -3409,6 +3421,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 	 */
 	intel_pch_reset_handshake(dev_priv, false);
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	/* Enable PG1 */
 	mutex_lock(&power_domains->lock);
 
@@ -3430,6 +3445,9 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	gen9_dbuf_disable(dev_priv);
@@ -3463,6 +3481,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 	/* 1. Enable PCH Reset Handshake */
 	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	/* 2-3. */
 	cnl_combo_phys_init(dev_priv);
 
@@ -3490,9 +3511,12 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* 1. Disable all display engine functions -> aready done */
+	/* 1. Disable all display engine functions -> already done */
 
 	/* 2. Disable DBUF */
 	gen9_dbuf_disable(dev_priv);
@@ -3527,6 +3551,9 @@ void icl_display_core_init(struct drm_i915_private *dev_priv,
 	/* 1. Enable PCH reset handshake. */
 	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	/* 2-3. */
 	icl_combo_phys_init(dev_priv);
 
@@ -3557,9 +3584,12 @@ void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	/* 1. Disable all display engine functions -> aready done */
+	/* 1. Disable all display engine functions -> already done */
 
 	/* 2. Disable DBUF */
 	icl_dbuf_disable(dev_priv);
@@ -3588,6 +3618,9 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
 	struct i915_power_well *cmn_d =
 		lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	/*
 	 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
 	 * workaround never ever read DISPLAY_PHY_CONTROL, and
@@ -3675,6 +3708,9 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
 	struct i915_power_well *disp2d =
 		lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
 
+	if (!HAS_DISPLAY(dev_priv))
+		return;
+
 	/* If the display might be already active skip this */
 	if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
 	    disp2d->desc->ops->is_enabled(dev_priv, disp2d) &&
-- 
2.19.1