[PATCH 3/7] drm/i915: Move all runtime modified device info fields into runtime info
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Mon Nov 12 14:30:47 UTC 2018
From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
After the previous change which cleared the static tables from effectively
unused storage, we now replicate entries which have defaults set from
there, but can be overriden at runtime.
For this class of variables all accessor macros and call sites are changed
to use the runtime version.
Therefore at driver load time we need to copy over these variables from
static to the runtime table.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 38 ++++--
drivers/gpu/drm/i915/i915_drv.h | 18 +--
drivers/gpu/drm/i915/i915_gem.c | 5 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 114 +++++++++---------
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 24 ++--
drivers/gpu/drm/i915/intel_device_info.h | 30 +++--
drivers/gpu/drm/i915/intel_display.c | 18 +--
drivers/gpu/drm/i915/intel_display.h | 4 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_fbdev.c | 4 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 9 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 18 +--
drivers/gpu/drm/i915/selftests/intel_guc.c | 4 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 11 +-
22 files changed, 175 insertions(+), 147 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1b8a3f203b92..74362a1fb2be 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -510,7 +510,7 @@ static int i915_gem_object_info(struct seq_file *m, void *data)
seq_printf(m, "%llu [%pa] gtt total\n",
ggtt->vm.total, &ggtt->mappable_end);
seq_printf(m, "Supported page sizes: %s\n",
- stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
+ stringify_page_sizes(dev_priv->runtime_info.page_sizes,
buf, sizeof(buf)));
seq_putc(m, '\n');
@@ -4144,7 +4144,7 @@ i915_ring_test_irq_set(void *data, u64 val)
if (INTEL_GEN(i915) >= 11)
return -ENODEV;
- val &= INTEL_INFO(i915)->ring_mask;
+ val &= i915->runtime_info.ring_mask;
DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9cfd5b145248..bbdd36119eae 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -287,7 +287,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
* Use PCH_NOP (PCH but no South Display) for PCH platforms without
* display.
*/
- if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
+ if (pch && dev_priv->runtime_info.num_pipes == 0) {
DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
dev_priv->pch_type = PCH_NOP;
dev_priv->pch_id = 0;
@@ -646,9 +646,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (i915_inject_load_failure())
return -ENODEV;
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (dev_priv->runtime_info.num_pipes) {
ret = drm_vblank_init(&dev_priv->drm,
- INTEL_INFO(dev_priv)->num_pipes);
+ dev_priv->runtime_info.num_pipes);
if (ret)
goto out;
}
@@ -697,7 +697,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_overlay_setup(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (dev_priv->runtime_info.num_pipes == 0)
return 0;
ret = intel_fbdev_init(dev);
@@ -1552,7 +1552,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
} else
DRM_ERROR("Failed to register driver for userspace access!\n");
- if (INTEL_INFO(dev_priv)->num_pipes) {
+ if (dev_priv->runtime_info.num_pipes) {
/* Must be done after probing outputs */
intel_opregion_register(dev_priv);
acpi_video_register();
@@ -1576,7 +1576,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
* We need to coordinate the hotplugs with the asynchronous fbdev
* configuration, for which we use the fbdev->async_cookie.
*/
- if (INTEL_INFO(dev_priv)->num_pipes)
+ if (dev_priv->runtime_info.num_pipes)
drm_kms_helper_poll_init(dev);
intel_power_domains_enable(dev_priv);
@@ -1637,6 +1637,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
{
const struct intel_device_info *match_info =
(struct intel_device_info *)ent->driver_data;
+ struct intel_runtime_device_info *runtime_info;
struct intel_device_info *device_info;
struct drm_i915_private *i915;
int err;
@@ -1658,11 +1659,30 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
/* Setup the write-once "constant" device info */
device_info = mkwrite_device_info(i915);
memcpy(device_info, match_info, sizeof(*device_info));
- device_info->device_id = pdev->device;
BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
BITS_PER_TYPE(device_info->platform_mask));
- BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
+ BUG_ON(device_info->__gen > BITS_PER_TYPE(device_info->gen_mask));
+
+ /*
+ * Early setup of the runtime device info.
+ */
+ runtime_info = &i915->runtime_info;
+
+ runtime_info->device_id = pdev->device;
+
+ /*
+ * Copy over entries that are both set statically but can also be
+ * modified at runtime.
+ */
+ runtime_info->gen = device_info->__gen;
+ runtime_info->has_fbc = device_info->__has_fbc;
+ runtime_info->has_rc6 = device_info->__has_rc6;
+ runtime_info->has_rc6p = device_info->__has_rc6p;
+ runtime_info->ppgtt = device_info->__ppgtt;
+ runtime_info->page_sizes = device_info->__page_sizes;
+ runtime_info->ring_mask = device_info->__ring_mask;
+ runtime_info->num_pipes = device_info->__num_pipes;
return i915;
}
@@ -1701,7 +1721,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
return PTR_ERR(dev_priv);
/* Disable nuclear pageflip by default on pre-ILK */
- if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
+ if (!i915_modparams.nuclear_pageflip && match_info->__gen < 5)
dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
ret = pci_enable_device(pdev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f677a9936d33..4fabbcd6cfb2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2210,7 +2210,7 @@ static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
/* Iterator over subset of engines selected by mask */
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
- for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
+ for ((tmp__) = (mask__) & (dev_priv__)->runtime_info.ring_mask; \
(tmp__) ? \
((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
0;)
@@ -2358,8 +2358,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define INTEL_INFO(dev_priv) intel_info((dev_priv))
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
-#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
-#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
+#define INTEL_GEN(dev_priv) ((dev_priv)->runtime_info.gen)
+#define INTEL_DEVID(dev_priv) ((dev_priv)->runtime_info.device_id)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
@@ -2557,7 +2557,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define ALL_ENGINES (~0)
#define HAS_ENGINE(dev_priv, id) \
- (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
+ (!!((dev_priv)->runtime_info.ring_mask & ENGINE_MASK(id)))
#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
@@ -2583,7 +2583,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT(dev_priv) ((dev_priv)->runtime_info.ppgtt)
#define HAS_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
@@ -2593,7 +2593,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
- ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
+ ((sizes) & ~(dev_priv)->runtime_info.page_sizes) == 0; \
})
#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
@@ -2623,7 +2623,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
-#define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
+#define HAS_FBC(dev_priv) ((dev_priv)->runtime_info.has_fbc)
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
@@ -2634,8 +2634,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
-#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
-#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
+#define HAS_RC6(dev_priv) ((dev_priv)->runtime_info.has_rc6)
+#define HAS_RC6p(dev_priv) ((dev_priv)->runtime_info.has_rc6p)
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c55b1f75c980..24fea3bc71d2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2725,7 +2725,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
unsigned int sg_page_sizes)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = i915->runtime_info.page_sizes;
int i;
lockdep_assert_held(&obj->mm.lock);
@@ -5535,8 +5535,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
/* We need to fallback to 4K pages if host doesn't support huge gtt. */
if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
- mkwrite_device_info(dev_priv)->page_sizes =
- I915_GTT_PAGE_SIZE_4K;
+ dev_priv->runtime_info.page_sizes = I915_GTT_PAGE_SIZE_4K;
dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a98c29147d5e..4fd4bc84996b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -799,7 +799,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
*/
static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
{
- ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->vm.i915)->ring_mask;
+ ppgtt->pd_dirty_rings = ppgtt->vm.i915->runtime_info.ring_mask;
}
/* Removes entries from a single page table, releasing it if it's empty.
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d447d7d508f4..8a243069f02a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3322,7 +3322,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
*/
intel_runtime_pm_get(dev_priv);
- engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
+ engine_mask &= dev_priv->runtime_info.ring_mask;
if (flags & I915_ERROR_CAPTURE) {
i915_capture_error_state(dev_priv, engine_mask, msg);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e6e7fcdf0ab7..8eb16c54648f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -30,7 +30,7 @@
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
-#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
+#define GEN(x) .__gen = (x), .gen_mask = BIT((x) - 1)
#define GEN_DEFAULT_PIPEOFFSETS \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
@@ -60,16 +60,16 @@
/* Keep in gen based order, and chronological order within a gen */
#define GEN_DEFAULT_PAGE_SIZES \
- .page_sizes = I915_GTT_PAGE_SIZE_4K
+ .__page_sizes = I915_GTT_PAGE_SIZE_4K
#define GEN2_FEATURES \
GEN(2), \
- .num_pipes = 1, \
+ .__num_pipes = 1, \
.has_overlay = 1, .overlay_needs_physical = 1, \
.has_gmch_display = 1, \
.hws_needs_physical = 1, \
.unfenced_needs_alignment = 1, \
- .ring_mask = RENDER_RING, \
+ .__ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -80,7 +80,7 @@ static const struct intel_device_info intel_i830_info = {
GEN2_FEATURES,
PLATFORM(INTEL_I830),
.is_mobile = 1, .cursor_needs_physical = 1,
- .num_pipes = 2, /* legal, last one wins */
+ .__num_pipes = 2, /* legal, last one wins */
};
static const struct intel_device_info intel_i845g_info = {
@@ -92,9 +92,9 @@ static const struct intel_device_info intel_i85x_info = {
GEN2_FEATURES,
PLATFORM(INTEL_I85X),
.is_mobile = 1,
- .num_pipes = 2, /* legal, last one wins */
+ .__num_pipes = 2, /* legal, last one wins */
.cursor_needs_physical = 1,
- .has_fbc = 1,
+ .__has_fbc = 1,
};
static const struct intel_device_info intel_i865g_info = {
@@ -104,9 +104,9 @@ static const struct intel_device_info intel_i865g_info = {
#define GEN3_FEATURES \
GEN(3), \
- .num_pipes = 2, \
+ .__num_pipes = 2, \
.has_gmch_display = 1, \
- .ring_mask = RENDER_RING, \
+ .__ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -130,7 +130,7 @@ static const struct intel_device_info intel_i915gm_info = {
.cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
- .has_fbc = 1,
+ .__has_fbc = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -151,7 +151,7 @@ static const struct intel_device_info intel_i945gm_info = {
.has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
- .has_fbc = 1,
+ .__has_fbc = 1,
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -173,10 +173,10 @@ static const struct intel_device_info intel_pineview_info = {
#define GEN4_FEATURES \
GEN(4), \
- .num_pipes = 2, \
+ .__num_pipes = 2, \
.has_hotplug = 1, \
.has_gmch_display = 1, \
- .ring_mask = RENDER_RING, \
+ .__ring_mask = RENDER_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -194,7 +194,7 @@ static const struct intel_device_info intel_i965g_info = {
static const struct intel_device_info intel_i965gm_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
- .is_mobile = 1, .has_fbc = 1,
+ .is_mobile = 1, .__has_fbc = 1,
.has_overlay = 1,
.supports_tv = 1,
.hws_needs_physical = 1,
@@ -204,26 +204,26 @@ static const struct intel_device_info intel_i965gm_info = {
static const struct intel_device_info intel_g45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_G45),
- .ring_mask = RENDER_RING | BSD_RING,
+ .__ring_mask = RENDER_RING | BSD_RING,
};
static const struct intel_device_info intel_gm45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_GM45),
- .is_mobile = 1, .has_fbc = 1,
+ .is_mobile = 1, .__has_fbc = 1,
.supports_tv = 1,
- .ring_mask = RENDER_RING | BSD_RING,
+ .__ring_mask = RENDER_RING | BSD_RING,
};
#define GEN5_FEATURES \
GEN(5), \
- .num_pipes = 2, \
+ .__num_pipes = 2, \
.has_hotplug = 1, \
- .ring_mask = RENDER_RING | BSD_RING, \
+ .__ring_mask = RENDER_RING | BSD_RING, \
.has_snoop = true, \
.has_coherent_ggtt = true, \
/* ilk does support rc6, but we do not implement [power] contexts */ \
- .has_rc6 = 0, \
+ .__has_rc6 = 0, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -236,20 +236,20 @@ static const struct intel_device_info intel_ironlake_d_info = {
static const struct intel_device_info intel_ironlake_m_info = {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
- .is_mobile = 1, .has_fbc = 1,
+ .is_mobile = 1, .__has_fbc = 1,
};
#define GEN6_FEATURES \
GEN(6), \
- .num_pipes = 2, \
+ .__num_pipes = 2, \
.has_hotplug = 1, \
- .has_fbc = 1, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .__has_fbc = 1, \
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_coherent_ggtt = true, \
.has_llc = 1, \
- .has_rc6 = 1, \
- .has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_ALIASING, \
+ .__has_rc6 = 1, \
+ .__has_rc6p = 1, \
+ .__ppgtt = INTEL_PPGTT_ALIASING, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -286,15 +286,15 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
#define GEN7_FEATURES \
GEN(7), \
- .num_pipes = 3, \
+ .__num_pipes = 3, \
.has_hotplug = 1, \
- .has_fbc = 1, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .__has_fbc = 1, \
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_coherent_ggtt = true, \
.has_llc = 1, \
- .has_rc6 = 1, \
- .has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_FULL, \
+ .__has_rc6 = 1, \
+ .__has_rc6p = 1, \
+ .__ppgtt = INTEL_PPGTT_FULL, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
@@ -334,7 +334,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
PLATFORM(INTEL_IVYBRIDGE),
.gt = 2,
- .num_pipes = 0, /* legal, last one wins */
+ .__num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
};
@@ -342,15 +342,15 @@ static const struct intel_device_info intel_valleyview_info = {
PLATFORM(INTEL_VALLEYVIEW),
GEN(7),
.is_lp = 1,
- .num_pipes = 2,
+ .__num_pipes = 2,
.has_runtime_pm = 1,
- .has_rc6 = 1,
+ .__has_rc6 = 1,
.has_gmch_display = 1,
.has_hotplug = 1,
- .ppgtt = INTEL_PPGTT_FULL,
+ .__ppgtt = INTEL_PPGTT_FULL,
.has_snoop = true,
.has_coherent_ggtt = false,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_PIPEOFFSETS,
@@ -359,12 +359,12 @@ static const struct intel_device_info intel_valleyview_info = {
#define G75_FEATURES \
GEN7_FEATURES, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
.has_ddi = 1, \
.has_fpga_dbg = 1, \
.has_psr = 1, \
.has_dp_mst = 1, \
- .has_rc6p = 0 /* RC6p removed-by HSW */, \
+ .__has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
#define HSW_PLATFORM \
@@ -391,10 +391,10 @@ static const struct intel_device_info intel_haswell_gt3_info = {
G75_FEATURES, \
GEN(8), \
BDW_COLORS, \
- .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ .__page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .__ppgtt = INTEL_PPGTT_FULL_4LVL, \
.has_64bit_reloc = 1, \
.has_reset_engine = 1
@@ -423,22 +423,22 @@ static const struct intel_device_info intel_broadwell_rsvd_info = {
static const struct intel_device_info intel_broadwell_gt3_info = {
BDW_PLATFORM,
.gt = 3,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
static const struct intel_device_info intel_cherryview_info = {
PLATFORM(INTEL_CHERRYVIEW),
GEN(8),
- .num_pipes = 3,
+ .__num_pipes = 3,
.has_hotplug = 1,
.is_lp = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.has_64bit_reloc = 1,
.has_runtime_pm = 1,
- .has_rc6 = 1,
+ .__has_rc6 = 1,
.has_logical_ring_contexts = 1,
.has_gmch_display = 1,
- .ppgtt = INTEL_PPGTT_FULL,
+ .__ppgtt = INTEL_PPGTT_FULL,
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
@@ -450,7 +450,7 @@ static const struct intel_device_info intel_cherryview_info = {
};
#define GEN9_DEFAULT_PAGE_SIZES \
- .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ .__page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_64K | \
I915_GTT_PAGE_SIZE_2M
@@ -482,7 +482,7 @@ static const struct intel_device_info intel_skylake_gt2_info = {
#define SKL_GT3_PLUS_PLATFORM \
SKL_PLATFORM, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
static const struct intel_device_info intel_skylake_gt3_info = {
@@ -499,21 +499,21 @@ static const struct intel_device_info intel_skylake_gt4_info = {
GEN(9), \
.is_lp = 1, \
.has_hotplug = 1, \
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
- .num_pipes = 3, \
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .__num_pipes = 3, \
.has_64bit_reloc = 1, \
.has_ddi = 1, \
.has_fpga_dbg = 1, \
- .has_fbc = 1, \
+ .__has_fbc = 1, \
.has_psr = 1, \
.has_runtime_pm = 1, \
.has_csr = 1, \
- .has_rc6 = 1, \
+ .__has_rc6 = 1, \
.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
.has_guc = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .__ppgtt = INTEL_PPGTT_FULL_4LVL, \
.has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
@@ -553,7 +553,7 @@ static const struct intel_device_info intel_kabylake_gt2_info = {
static const struct intel_device_info intel_kabylake_gt3_info = {
KBL_PLATFORM,
.gt = 3,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
#define CFL_PLATFORM \
@@ -573,7 +573,7 @@ static const struct intel_device_info intel_coffeelake_gt2_info = {
static const struct intel_device_info intel_coffeelake_gt3_info = {
CFL_PLATFORM,
.gt = 3,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
#define GEN10_FEATURES \
@@ -605,7 +605,7 @@ static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
.is_alpha_support = 1,
- .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
+ .__ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
};
#undef GEN
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 0ad2304457ab..c31bfac5201c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1721,7 +1721,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
const struct bdb_header *bdb;
u8 __iomem *bios = NULL;
- if (INTEL_INFO(dev_priv)->num_pipes == 0) {
+ if (dev_priv->runtime_info.num_pipes == 0) {
DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
return;
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8385767aaf08..aeb7b9225b18 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -131,7 +131,7 @@ void intel_device_info_dump(const struct intel_device_info *info,
INTEL_DEVID(dev_priv),
INTEL_REVID(dev_priv),
intel_platform_name(info->platform),
- info->gen);
+ info->__gen);
intel_device_info_dump_flags(info, p);
}
@@ -748,7 +748,6 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
*/
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
struct intel_runtime_device_info *runtime_info =
&dev_priv->runtime_info;
enum pipe pipe;
@@ -793,8 +792,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (i915_modparams.disable_display) {
DRM_INFO("Display disabled (module parameter)\n");
- info->num_pipes = 0;
- } else if (info->num_pipes > 0 &&
+ runtime_info->num_pipes = 0;
+ } else if (runtime_info->num_pipes > 0 &&
(IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
@@ -814,12 +813,12 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
(HAS_PCH_CPT(dev_priv) &&
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
DRM_INFO("Display fused off, disabling\n");
- info->num_pipes = 0;
+ runtime_info->num_pipes = 0;
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
DRM_INFO("PipeC fused off\n");
- info->num_pipes -= 1;
+ runtime_info->num_pipes -= 1;
}
- } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
+ } else if (runtime_info->num_pipes > 0 && IS_GEN9(dev_priv)) {
u32 dfsm = I915_READ(SKL_DFSM);
u8 disabled_mask = 0;
bool invalid;
@@ -845,11 +844,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
invalid = false;
}
- if (num_bits > info->num_pipes || invalid)
+ if (num_bits > runtime_info->num_pipes || invalid)
DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
disabled_mask);
else
- info->num_pipes -= num_bits;
+ runtime_info->num_pipes -= num_bits;
}
/* Initialize slice/subslice/EU info */
@@ -868,7 +867,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (IS_GEN6(dev_priv) && intel_vtd_active()) {
DRM_INFO("Disabling ppGTT for VT-d support\n");
- info->ppgtt = INTEL_PPGTT_NONE;
+ runtime_info->ppgtt = INTEL_PPGTT_NONE;
}
/* Initialize command stream timestamp frequency */
@@ -892,7 +891,6 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
*/
void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
struct intel_runtime_device_info *runtime_info =
&dev_priv->runtime_info;
u32 media_fuse;
@@ -914,7 +912,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
continue;
if (!(BIT(i) & runtime_info->vdbox_enable)) {
- info->ring_mask &= ~ENGINE_MASK(_VCS(i));
+ runtime_info->ring_mask &= ~ENGINE_MASK(_VCS(i));
DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
}
}
@@ -925,7 +923,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
continue;
if (!(BIT(i) & runtime_info->vebox_enable)) {
- info->ring_mask &= ~ENGINE_MASK(_VECS(i));
+ runtime_info->ring_mask &= ~ENGINE_MASK(_VECS(i));
DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
}
}
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 83e19ac8e401..50c8fda20bdd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -93,7 +93,7 @@ enum intel_ppgtt {
func(has_ddi); \
func(has_dp_mst); \
func(has_reset_engine); \
- func(has_fbc); \
+ func(__has_fbc); \
func(has_fpga_dbg); \
func(has_gmch_display); \
func(has_guc); \
@@ -106,8 +106,8 @@ enum intel_ppgtt {
func(has_logical_ring_preemption); \
func(has_overlay); \
func(has_psr); \
- func(has_rc6); \
- func(has_rc6p); \
+ func(__has_rc6); \
+ func(__has_rc6p); \
func(has_runtime_pm); \
func(has_snoop); \
func(has_coherent_ggtt); \
@@ -148,19 +148,18 @@ struct sseu_dev_info {
typedef u8 intel_ring_mask_t;
struct intel_device_info {
- u16 device_id;
u16 gen_mask;
- u8 gen;
+ u8 __gen;
u8 gt; /* GT number, 0 if undefined */
- intel_ring_mask_t ring_mask; /* Rings supported by the HW */
- u8 num_pipes;
+ intel_ring_mask_t __ring_mask; /* Rings supported by the HW */
+ u8 __num_pipes;
enum intel_platform platform;
u32 platform_mask;
- enum intel_ppgtt ppgtt;
- unsigned int page_sizes; /* page sizes supported by the HW */
+ enum intel_ppgtt __ppgtt;
+ unsigned int __page_sizes; /* page sizes supported by the HW */
u32 display_mmio_offset;
@@ -181,11 +180,24 @@ struct intel_device_info {
};
#define DEV_RUNTIME_INFO_FOR_EACH_FLAG(func) \
+ func(has_fbc); \
func(has_pooled_eu); \
+ func(has_rc6); \
+ func(has_rc6p); \
struct intel_runtime_device_info {
+ int gen;
+
unsigned int num_rings;
+ enum intel_ppgtt ppgtt;
+ unsigned int page_sizes; /* page sizes supported by the HW */
+
+ u16 device_id;
+
+ intel_ring_mask_t ring_mask; /* Rings supported by the HW */
+ u8 num_pipes;
+
u8 num_sprites[I915_MAX_PIPES];
u8 num_scalers[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cc30bf1172ad..e87f4fc648de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6372,7 +6372,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
}
}
- if (INTEL_INFO(dev_priv)->num_pipes == 2)
+ if (dev_priv->runtime_info.num_pipes == 2)
return 0;
/* Ivybridge 3 pipe is really complicated */
@@ -8588,7 +8588,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
* clear if it''s a win or loss power wise. No point in doing
* this on ILK at all since it has a fixed DPLL<->pipe mapping.
*/
- if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
+ if (dev_priv->runtime_info.num_pipes == 3 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
dpll |= DPLL_SDVO_HIGH_SPEED;
@@ -12684,7 +12684,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state)
if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
entries,
- INTEL_INFO(dev_priv)->num_pipes, i))
+ dev_priv->runtime_info.num_pipes, i))
continue;
updated |= cmask;
@@ -14111,7 +14111,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_pps_init(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (dev_priv->runtime_info.num_pipes == 0)
return;
/*
@@ -15063,8 +15063,8 @@ int intel_modeset_init(struct drm_device *dev)
dev->mode_config.fb_base = ggtt->gmadr.start;
DRM_DEBUG_KMS("%d display pipe%s available.\n",
- INTEL_INFO(dev_priv)->num_pipes,
- INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
+ dev_priv->runtime_info.num_pipes,
+ dev_priv->runtime_info.num_pipes > 1 ? "s" : "");
for_each_pipe(dev_priv, pipe) {
ret = intel_crtc_init(dev_priv, pipe);
@@ -15983,7 +15983,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
};
int i;
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (dev_priv->runtime_info.num_pipes == 0)
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
@@ -16024,7 +16024,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
}
/* Note: this does not include DSI transcoders. */
- error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
+ error->num_transcoders = dev_priv->runtime_info.num_pipes;
if (HAS_DDI(dev_priv))
error->num_transcoders++; /* Account for eDP. */
@@ -16063,7 +16063,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
if (!error)
return;
- err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
+ err_printf(m, "Num Pipes: %d\n", dev_priv->runtime_info.num_pipes);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
err_printf(m, "PWR_WELL_CTL2: %08x\n",
error->power_well_driver);
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 607ddc4a0b11..00ef394f08d5 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -282,10 +282,10 @@ struct intel_link_m_n {
};
#define for_each_pipe(__dev_priv, __p) \
- for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
+ for ((__p) = 0; (__p) < (__dev_priv)->runtime_info.num_pipes; (__p)++)
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
- for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
+ for ((__p) = 0; (__p) < (__dev_priv)->runtime_info.num_pipes; (__p)++) \
for_each_if((__mask) & BIT(__p))
#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index b464ee0afb85..ea21bf6730ed 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -325,8 +325,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
*/
int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
- const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
+ const unsigned int ring_mask = dev_priv->runtime_info.ring_mask;
struct intel_engine_cs *engine;
enum intel_engine_id id;
unsigned int mask = 0;
@@ -357,7 +356,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
* engines.
*/
if (WARN_ON(mask != ring_mask))
- device_info->ring_mask = mask;
+ dev_priv->runtime_info.ring_mask = mask;
/* We always presume we have at least RCS available for later probing */
if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) {
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 14cbaf4a0e93..fe925abd1c7a 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1309,7 +1309,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
fbc->active = false;
if (need_fbc_vtd_wa(dev_priv))
- mkwrite_device_info(dev_priv)->has_fbc = false;
+ dev_priv->runtime_info.has_fbc = false;
i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 2480c7d6edee..e3b8f9cf0f25 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -484,7 +484,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
* fbdev helper library.
*/
if (num_connectors_enabled != num_connectors_detected &&
- num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
+ num_connectors_enabled < dev_priv->runtime_info.num_pipes) {
DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
num_connectors_detected);
@@ -672,7 +672,7 @@ int intel_fbdev_init(struct drm_device *dev)
struct intel_fbdev *ifbdev;
int ret;
- if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
+ if (WARN_ON(dev_priv->runtime_info.num_pipes == 0))
return -ENODEV;
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 1570dcbe249c..dfe4a5ef1784 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1024,7 +1024,7 @@ static int guc_clients_create(struct intel_guc *guc)
GEM_BUG_ON(guc->preempt_client);
client = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ dev_priv->runtime_info.ring_mask,
GUC_CLIENT_PRIORITY_KMD_NORMAL,
dev_priv->kernel_context);
if (IS_ERR(client)) {
@@ -1035,7 +1035,7 @@ static int guc_clients_create(struct intel_guc *guc)
if (dev_priv->preempt_context) {
client = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ dev_priv->runtime_info.ring_mask,
GUC_CLIENT_PRIORITY_KMD_HIGH,
dev_priv->preempt_context);
if (IS_ERR(client)) {
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 33d87ab93fdd..5543597ec74a 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -817,7 +817,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
unsigned int pin;
int ret;
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
+ if (dev_priv->runtime_info.num_pipes == 0)
return 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_lpe_audio.c b/drivers/gpu/drm/i915/intel_lpe_audio.c
index 5d5336fbe7b0..22fa3277ee59 100644
--- a/drivers/gpu/drm/i915/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/intel_lpe_audio.c
@@ -111,7 +111,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
pinfo.size_data = sizeof(*pdata);
pinfo.dma_mask = DMA_BIT_MASK(32);
- pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes;
+ pdata->num_pipes = dev_priv->runtime_info.num_pipes;
pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */
pdata->port[0].pipe = -1;
pdata->port[1].pipe = -1;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 17270d8f1880..176a4a19377e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1899,7 +1899,8 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
for (level = 0; level < wm_state->num_levels; level++) {
const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
- const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
+ const int sr_fifo_size =
+ dev_priv->runtime_info.num_pipes * 512 - 1;
if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
break;
@@ -2632,7 +2633,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
/* HSW allows LP1+ watermarks even with multiple pipes */
if (level == 0 || config->num_pipes_active > 1) {
- fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
+ fifo_size /= dev_priv->runtime_info.num_pipes;
/*
* For some reason the non self refresh
@@ -6886,7 +6887,7 @@ static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
static bool sanitize_rc6(struct drm_i915_private *i915)
{
- struct intel_device_info *info = mkwrite_device_info(i915);
+ struct intel_runtime_device_info *info = &i915->runtime_info;
/* Powersaving is controlled by the host when inside a VM */
if (intel_vgpu_active(i915))
@@ -9498,7 +9499,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (IS_GEN2(dev_priv)) {
- if (INTEL_INFO(dev_priv)->num_pipes == 1) {
+ if (dev_priv->runtime_info.num_pipes == 1) {
dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size;
} else {
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 26c065c8d2c0..935ded51adc0 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -341,7 +341,7 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single)
static int igt_check_page_sizes(struct i915_vma *vma)
{
struct drm_i915_private *i915 = vma->vm->i915;
- unsigned int supported = INTEL_INFO(i915)->page_sizes;
+ unsigned int supported = i915->runtime_info.page_sizes;
struct drm_i915_gem_object *obj = vma->obj;
int err = 0;
@@ -382,7 +382,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
{
struct i915_hw_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->vm.i915;
- unsigned int saved_mask = INTEL_INFO(i915)->page_sizes;
+ unsigned int saved_mask = i915->runtime_info.page_sizes;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
int i, j, single;
@@ -401,7 +401,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
combination |= page_sizes[j];
}
- mkwrite_device_info(i915)->page_sizes = combination;
+ i915->runtime_info.page_sizes = combination;
for (single = 0; single <= 1; ++single) {
obj = fake_huge_pages_object(i915, combination, !!single);
@@ -452,7 +452,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg)
out_put:
i915_gem_object_put(obj);
out_device:
- mkwrite_device_info(i915)->page_sizes = saved_mask;
+ i915->runtime_info.page_sizes = saved_mask;
return err;
}
@@ -461,7 +461,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
{
struct i915_hw_ppgtt *ppgtt = arg;
struct drm_i915_private *i915 = ppgtt->vm.i915;
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = i915->runtime_info.page_sizes;
struct drm_i915_gem_object *obj;
int bit;
int err;
@@ -1204,7 +1204,7 @@ static int igt_ppgtt_exhaust_huge(void *arg)
{
struct i915_gem_context *ctx = arg;
struct drm_i915_private *i915 = ctx->i915;
- unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ unsigned long supported = i915->runtime_info.page_sizes;
static unsigned int pages[ARRAY_SIZE(page_sizes)];
struct drm_i915_gem_object *obj;
unsigned int size_mask;
@@ -1296,7 +1296,7 @@ static int igt_ppgtt_exhaust_huge(void *arg)
i915_gem_object_unpin_pages(obj);
i915_gem_object_put(obj);
out_device:
- mkwrite_device_info(i915)->page_sizes = supported;
+ i915->runtime_info.page_sizes = supported;
return err;
}
@@ -1434,7 +1434,7 @@ static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
struct drm_i915_private *dev_priv = ctx->i915;
- unsigned long supported = INTEL_INFO(dev_priv)->page_sizes;
+ unsigned long supported = dev_priv->runtime_info.page_sizes;
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
@@ -1711,7 +1711,7 @@ int i915_gem_huge_page_mock_selftests(void)
return -ENOMEM;
/* Pretend to be a device which supports the 48b PPGTT */
- mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+ dev_priv->runtime_info.ppgtt = INTEL_PPGTT_FULL_4LVL;
pdev = dev_priv->drm.pdev;
dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c
index 32cba4cae31a..65e5e8a64ce2 100644
--- a/drivers/gpu/drm/i915/selftests/intel_guc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
@@ -111,7 +111,7 @@ static int validate_client(struct intel_guc_client *client,
dev_priv->preempt_context : dev_priv->kernel_context;
if (client->owner != ctx_owner ||
- client->engines != INTEL_INFO(dev_priv)->ring_mask ||
+ client->engines != dev_priv->runtime_info.ring_mask ||
client->priority != client_priority ||
client->doorbell_id == GUC_DOORBELL_INVALID)
return -EINVAL;
@@ -259,7 +259,7 @@ static int igt_guc_doorbells(void *arg)
for (i = 0; i < ATTEMPTS; i++) {
clients[i] = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->ring_mask,
+ dev_priv->runtime_info.ring_mask,
i % GUC_CLIENT_PRIORITY_NUM,
dev_priv->kernel_context);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..b6849ca11e01 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -174,12 +174,11 @@ struct drm_i915_private *mock_gem_device(void)
/* Using the global GTT may ask questions about KMS users, so prepare */
drm_mode_config_init(&i915->drm);
- mkwrite_device_info(i915)->gen = -1;
+ i915->runtime_info.gen = -1;
- mkwrite_device_info(i915)->page_sizes =
- I915_GTT_PAGE_SIZE_4K |
- I915_GTT_PAGE_SIZE_64K |
- I915_GTT_PAGE_SIZE_2M;
+ i915->runtime_info.page_sizes = I915_GTT_PAGE_SIZE_4K |
+ I915_GTT_PAGE_SIZE_64K |
+ I915_GTT_PAGE_SIZE_2M;
mock_uncore_init(i915);
i915_gem_init__mm(i915);
@@ -231,7 +230,7 @@ struct drm_i915_private *mock_gem_device(void)
mock_init_ggtt(i915);
- mkwrite_device_info(i915)->ring_mask = BIT(0);
+ i915->runtime_info.ring_mask = BIT(0);
i915->kernel_context = mock_context(i915, NULL);
if (!i915->kernel_context)
goto err_unlock;
--
2.19.1
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