[PATCH] wip: drm/i915: Nuke PCH_NOP
José Roberto de Souza
jose.souza at intel.com
Thu Nov 15 22:38:07 UTC 2018
The only part of north bridge or PCH north that matters for i915 is
the display engine and if a GEN(IVB I'm looking at you) don't have
the display engine, num_pipes is set to 0 so the display block
is not initialized and then pch_type is set to PCH_NOP.
In the case of the Atom processors(VLV, CHV and BXT) that have PCH
south functions embedded in the SOC is was already being handle as
PCH_NONE/HAS_PCH_SPLIT().
Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 9 +++------
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_irq.c | 15 +++++++--------
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++++----
5 files changed, 15 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b1d23c73c147..841ac858e484 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -283,13 +283,10 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
}
}
- /*
- * Use PCH_NOP (PCH but no South Display) for PCH platforms without
- * display.
- */
+ /* Set PCH_NONE for GENs without display */
if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
- DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
- dev_priv->pch_type = PCH_NOP;
+ DRM_DEBUG_KMS("Display disabled, reverting to PCH_NONE\n");
+ dev_priv->pch_type = PCH_NONE;
dev_priv->pch_id = 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d69b71d368d3..15177970bdf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -652,7 +652,6 @@ enum intel_pch {
PCH_KBP, /* Kaby Lake PCH */
PCH_CNP, /* Cannon Lake PCH */
PCH_ICP, /* Ice Lake PCH */
- PCH_NOP, /* PCH without south display */
};
enum intel_sbi_destination {
@@ -2691,7 +2690,6 @@ intel_info(const struct drm_i915_private *dev_priv)
INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
-#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d447d7d508f4..540b753169af 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2582,7 +2582,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
}
/* check event from PCH */
- if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
+ if (HAS_PCH_SPLIT(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
u32 pch_iir = I915_READ(SDEIIR);
cpt_irq_handler(dev_priv, pch_iir);
@@ -2622,7 +2622,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
* able to process them after we restore SDEIER (as soon as we restore
* it, we'll get an interrupt if SDEIIR still has something to process
* due to its back queue). */
- if (!HAS_PCH_NOP(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev_priv)) {
sde_ier = I915_READ(SDEIER);
I915_WRITE(SDEIER, 0);
}
@@ -2659,7 +2659,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
}
I915_WRITE(DEIER, de_ier);
- if (!HAS_PCH_NOP(dev_priv))
+ if (HAS_PCH_SPLIT(dev_priv))
I915_WRITE(SDEIER, sde_ier);
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
@@ -2855,8 +2855,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
fault_errors);
}
- if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
- master_ctl & GEN8_DE_PCH_IRQ) {
+ if (HAS_PCH_SPLIT(dev_priv) && master_ctl & GEN8_DE_PCH_IRQ) {
/*
* FIXME(BDW): Assume for now that the new interrupt handling
* scheme also closed the SDE interrupt handling race we've seen
@@ -3499,7 +3498,7 @@ static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_NOP(dev_priv))
+ if (!HAS_PCH_SPLIT(dev_priv))
return;
GEN3_IRQ_RESET(SDE);
@@ -3520,7 +3519,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (HAS_PCH_NOP(dev_priv))
+ if (!HAS_PCH_SPLIT(dev_priv))
return;
WARN_ON(I915_READ(SDEIER) != 0);
@@ -4010,7 +4009,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
u32 mask;
- if (HAS_PCH_NOP(dev_priv))
+ if (!HAS_PCH_SPLIT(dev_priv))
return;
if (HAS_PCH_IBX(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27498ded4949..9dff667553c5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9141,7 +9141,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
snpcr |= GEN6_MBC_SNPCR_MED;
I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
- if (!HAS_PCH_NOP(dev_priv))
+ if (HAS_PCH_SPLIT(dev_priv))
cpt_init_clock_gating(dev_priv);
gen6_check_mch_setup(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index acb5393a046b..91c6b57bea90 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3352,7 +3352,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* enable PCH reset handshake */
- intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ intel_pch_reset_handshake(dev_priv, HAS_PCH_SPLIT(dev_priv));
/* enable PG1 and Misc I/O */
mutex_lock(&power_domains->lock);
@@ -3471,7 +3471,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* 1. Enable PCH Reset Handshake */
- intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ intel_pch_reset_handshake(dev_priv, HAS_PCH_SPLIT(dev_priv));
/* 2-3. */
cnl_combo_phys_init(dev_priv);
@@ -3535,7 +3535,7 @@ void icl_display_core_init(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* 1. Enable PCH reset handshake. */
- intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ intel_pch_reset_handshake(dev_priv, HAS_PCH_SPLIT(dev_priv));
/* 2-3. */
icl_combo_phys_init(dev_priv);
@@ -3747,7 +3747,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
vlv_cmnlane_wa(dev_priv);
mutex_unlock(&power_domains->lock);
} else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
- intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ intel_pch_reset_handshake(dev_priv, HAS_PCH_SPLIT(dev_priv));
/*
* Keep all power wells enabled for any dependent HW access during
--
2.19.1
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