[PATCH 2/3] barrier-after-pdp

[Chris Wilson]

---
 drivers/gpu/drm/i915/intel_lrc.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 08fd9b12e4d7..c6691fcc04ab 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -386,7 +386,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (!i915_vm_is_48bit(&ppgtt->vm))
+	if (!i915_vm_is_48bit(&ppgtt->vm) && intel_vgpu_active(rq->i915))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	/*
@@ -1836,7 +1836,7 @@ static void execlists_reset_finish(struct intel_engine_cs *engine)
 		  atomic_read(&execlists->tasklet.count));
 }
 
-static int intel_logical_ring_emit_pdps(struct i915_request *rq)
+static int emit_pdps(struct i915_request *rq)
 {
 	struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
 	struct intel_engine_cs *engine = rq->engine;
@@ -1844,12 +1844,15 @@ static int intel_logical_ring_emit_pdps(struct i915_request *rq)
 	u32 *cs;
 	int i;
 
+	if (!(ppgtt->pd_dirty_rings & intel_engine_flag(engine)))
+		return 0;
+
 	cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2);
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
-	*cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
-	for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
+	*cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds) | MI_LRI_FORCE_POSTED;
+	for (i = GEN8_3LVL_PDPES; i--; ) {
 		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 
 		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
@@ -1861,6 +1864,7 @@ static int intel_logical_ring_emit_pdps(struct i915_request *rq)
 	*cs++ = MI_NOOP;
 	intel_ring_advance(rq, cs);
 
+	ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
 	return 0;
 }
 
@@ -1877,14 +1881,15 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * it is unsafe in case of lite-restore (because the ctx is
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
-	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	if (!i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
-		ret = intel_logical_ring_emit_pdps(rq);
+		ret = emit_pdps(rq);
 		if (ret)
 			return ret;
 
-		rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
+		ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+		if (ret)
+			return ret;
 	}
 
 	cs = intel_ring_begin(rq, 6);
-- 
2.20.0.rc1