[PATCH 5/6] eng wa
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Wed Nov 28 09:10:33 UTC 2018
From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +
drivers/gpu/drm/i915/intel_workarounds.c | 397 ++++++++++++++---------
drivers/gpu/drm/i915/intel_workarounds.h | 21 ++
4 files changed, 262 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 08fd9b12e4d7..c0934b713cef 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1629,6 +1629,8 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine)
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
+ i915_engine_workarounds_apply(engine);
+
intel_mocs_init_engine(engine);
intel_engine_reset_breadcrumbs(engine);
@@ -2326,6 +2328,8 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
ret);
}
+ i915_engine_workarounds_init(engine);
+
return 0;
err_cleanup_common:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8a2270b209b0..0d8b20ba7118 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -15,6 +15,7 @@
#include "i915_selftest.h"
#include "i915_timeline.h"
#include "intel_gpu_commands.h"
+#include "intel_workarounds.h"
struct drm_printer;
struct i915_sched_attr;
@@ -451,6 +452,7 @@ struct intel_engine_cs {
struct intel_hw_status_page status_page;
struct i915_ctx_workarounds wa_ctx;
+ struct i915_engine_workarounds wa_engine;
struct i915_vma *scratch;
u32 irq_keep_mask; /* always keep these interrupts */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 321ac0da8f63..0d3c582f8eea 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -608,32 +608,6 @@ wa_verify_bits(i915_reg_t reg, u32 cur, u32 mask, u32 val, const char *verify,
}
}
-static void
-wa_write(struct drm_i915_private *dev_priv, i915_reg_t reg, u32 val,
- const char *verify)
-{
- if (verify) {
- u32 mask = ~(~0 << fls(val));
-
- wa_verify_bits(reg, I915_READ(reg), mask, val, verify,
- __func__, true);
- } else {
- I915_WRITE(reg, val);
- }
-}
-
-static void
-wa_masked_en(struct drm_i915_private *dev_priv, i915_reg_t reg, u32 val,
- const char *verify)
-{
- if (verify) {
- wa_verify_bits(reg, I915_READ(reg), 0xffff, val, verify,
- __func__, false);
- } else {
- I915_WRITE(reg, _MASKED_BIT_ENABLE(val));
- }
-}
-
static void
wa_write_or(struct drm_i915_private *dev_priv, i915_reg_t reg, u32 val,
const char *verify)
@@ -673,19 +647,6 @@ chv_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
static void
gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
{
- /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
- wa_masked_en(dev_priv,
- GEN9_CSFE_CHICKEN1_RCS,
- GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE,
- verify);
-
-
- /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
- wa_write_or(dev_priv,
- BDW_SCRATCH1,
- GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE,
- verify);
-
/* WaDisableKillLogic:bxt,skl,kbl */
if (!IS_COFFEELAKE(dev_priv))
wa_write_or(dev_priv,
@@ -710,27 +671,6 @@ gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
GAM_ECOCHK,
BDW_DISABLE_HDC_INVALIDATION,
verify);
-
- /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
- if (IS_GEN9_LP(dev_priv))
- wa_write_masked_or(dev_priv,
- GEN8_L3SQCREG1,
- ~L3_PRIO_CREDITS_MASK,
- L3_GENERAL_PRIO_CREDITS(62) |
- L3_HIGH_PRIO_CREDITS(2),
- verify);
-
- /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
- wa_write_or(dev_priv,
- GEN8_L3SQCREG4,
- GEN8_LQSC_FLUSH_COHERENT_LINES,
- verify);
-
- /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
- wa_masked_en(dev_priv,
- GEN7_FF_SLICE_CS_CHICKEN1,
- GEN9_FFSC_PERCTX_PREEMPT_CTRL,
- verify);
}
static void
@@ -738,12 +678,6 @@ skl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
{
gen9_gt_workarounds_apply(dev_priv, verify);
- /* WaEnableGapsTsvCreditFix:skl */
- wa_write_or(dev_priv,
- GEN8_GARBCNTL,
- GEN9_GAPS_TSV_CREDIT_DISABLE,
- verify);
-
/* WaDisableGafsUnitClkGating:skl */
wa_write_or(dev_priv,
GEN7_UCGCTL4,
@@ -763,12 +697,6 @@ bxt_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
{
gen9_gt_workarounds_apply(dev_priv, verify);
- /* WaDisablePooledEuLoadBalancingFix:bxt */
- wa_masked_en(dev_priv,
- FF_SLICE_CS_CHICKEN2,
- GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE,
- verify);
-
/* WaInPlaceDecompressionHang:bxt */
wa_write_or(dev_priv,
GEN9_GAMT_ECO_REG_RW_IA,
@@ -781,12 +709,6 @@ kbl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
{
gen9_gt_workarounds_apply(dev_priv, verify);
- /* WaEnableGapsTsvCreditFix:kbl */
- wa_write_or(dev_priv,
- GEN8_GARBCNTL,
- GEN9_GAPS_TSV_CREDIT_DISABLE,
- verify);
-
/* WaDisableDynamicCreditSharing:kbl */
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
wa_write_or(dev_priv,
@@ -805,22 +727,6 @@ kbl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS,
verify);
-
- /* WaKBLVECSSemaphoreWaitPoll:kbl */
- if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_E0)) {
- struct intel_engine_cs *engine;
- unsigned int tmp;
-
- for_each_engine(engine, dev_priv, tmp) {
- if (engine->id == RCS)
- continue;
-
- wa_write(dev_priv,
- RING_SEMA_WAIT_POLL(engine->mmio_base),
- 1,
- verify);
- }
- }
}
static void
@@ -834,12 +740,6 @@ cfl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
{
gen9_gt_workarounds_apply(dev_priv, verify);
- /* WaEnableGapsTsvCreditFix:cfl */
- wa_write_or(dev_priv,
- GEN8_GARBCNTL,
- GEN9_GAPS_TSV_CREDIT_DISABLE,
- verify);
-
/* WaDisableGafsUnitClkGating:cfl */
wa_write_or(dev_priv,
GEN7_UCGCTL4,
@@ -934,12 +834,6 @@ cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS,
verify);
-
- /* WaEnablePreemptionGranularityControlByUMD:cnl */
- wa_masked_en(dev_priv,
- GEN7_FF_SLICE_CS_CHICKEN1,
- GEN9_FFSC_PERCTX_PREEMPT_CTRL,
- verify);
}
static void
@@ -947,46 +841,12 @@ icl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
{
wa_init_mcr(dev_priv, verify);
- /* This is not an Wa. Enable for better image quality */
- wa_masked_en(dev_priv,
- _3D_CHICKEN3,
- _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE,
- verify);
-
/* WaInPlaceDecompressionHang:icl */
wa_write_or(dev_priv,
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS,
verify);
- /* WaPipelineFlushCoherentLines:icl */
- wa_write_or(dev_priv,
- GEN8_L3SQCREG4,
- GEN8_LQSC_FLUSH_COHERENT_LINES,
- verify);
-
- /* Wa_1405543622:icl
- * Formerly known as WaGAPZPriorityScheme
- */
- wa_write_or(dev_priv,
- GEN8_GARBCNTL,
- GEN11_ARBITRATION_PRIO_ORDER_MASK,
- verify);
-
- /* Wa_1604223664:icl
- * Formerly known as WaL3BankAddressHashing
- */
- wa_write_masked_or(dev_priv,
- GEN8_GARBCNTL,
- ~GEN11_HASH_CTRL_EXCL_MASK,
- GEN11_HASH_CTRL_EXCL_BIT0,
- verify);
- wa_write_masked_or(dev_priv,
- GEN11_GLBLINVL,
- ~GEN11_BANK_HASH_ADDR_EXCL_MASK,
- GEN11_BANK_HASH_ADDR_EXCL_BIT0,
- verify);
-
/* WaModifyGamTlbPartitioning:icl */
wa_write_masked_or(dev_priv,
GEN11_GACB_PERF_CTRL,
@@ -994,14 +854,6 @@ icl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4,
verify);
- /* Wa_1405733216:icl
- * Formerly known as WaDisableCleanEvicts
- */
- wa_write_or(dev_priv,
- GEN8_L3SQCREG4,
- GEN11_LQSC_CLEAN_EVICT_DISABLE,
- verify);
-
/* Wa_1405766107:icl
* Formerly known as WaCL2SFHalfMaxAlloc
*/
@@ -1032,12 +884,6 @@ icl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
GWUNIT_CLKGATE_DIS,
verify);
- /* Wa_1604302699:icl */
- wa_write_or(dev_priv,
- GEN10_L3_CHICKEN_MODE_REGISTER,
- GEN11_I2M_WRITE_DISABLE,
- verify);
-
/* Wa_1406838659:icl (pre-prod) */
if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
wa_write_or(dev_priv,
@@ -1045,14 +891,6 @@ icl_gt_workarounds_apply(struct drm_i915_private *dev_priv, const char *verify)
CGPSF_CLKGATE_DIS,
verify);
- /* WaForwardProgressSoftReset:icl */
- wa_write_or(dev_priv,
- GEN10_SCRATCH_LNCF2,
- PMFLUSHDONE_LNICRSDROP |
- PMFLUSH_GAPL3UNBLOCK |
- PMFLUSHDONE_LNEBLK,
- verify);
-
/* Wa_1406463099:icl
* Formerly known as WaGamTlbPendError
*/
@@ -1258,6 +1096,241 @@ void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
whitelist_apply(engine, whitelist_build(engine, &w));
}
+static void
+wa_eng(struct i915_engine_workarounds *wa, const struct i915_engine_wa *reg)
+{
+ const unsigned int grow = 4;
+
+ if (wa->__size == wa->count) {
+ struct i915_engine_wa *regs;
+
+ regs = kcalloc(wa->__size + grow, sizeof(*reg), GFP_KERNEL);
+ if (!regs) {
+ DRM_ERROR("No space for workaround init!\n");
+ return;
+ }
+
+ if (wa->regs)
+ memcpy(regs, wa->regs, sizeof(*reg) * wa->count);
+
+ wa->regs = regs;
+ wa->__size += grow;
+ }
+
+ memcpy(&wa->regs[wa->count], reg, sizeof(*reg));
+ wa->count++;
+printk("+wa_eng: type=%u reg=%x mask=%x val=%x\n",
+ reg->type, i915_mmio_reg_offset(reg->reg), reg->mask, reg->val);
+}
+
+#define WA_ENG(__type, __reg, __mask, __val) \
+ &((struct i915_engine_wa) { \
+ .type = (__type), \
+ .reg = (__reg), \
+ .mask = (__mask), \
+ .val = (__val) \
+ })
+
+static void rcs_engine_wa_init(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *i915 = engine->i915;
+ struct i915_engine_workarounds *wa = &engine->wa_engine;
+
+ if (IS_GEN9(i915)) {
+ /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
+ if (IS_GEN9_LP(i915))
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN8_L3SQCREG1,
+ L3_PRIO_CREDITS_MASK,
+ L3_GENERAL_PRIO_CREDITS(62) |
+ L3_HIGH_PRIO_CREDITS(2)));
+
+ /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN8_L3SQCREG4,
+ 0,
+ GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+ /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ BDW_SCRATCH1,
+ 0,
+ GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE));
+
+ /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
+ wa_eng(wa, WA_ENG(I915_WA_MASKED,
+ GEN9_CSFE_CHICKEN1_RCS,
+ 0,
+ GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
+ }
+
+ if (IS_BROXTON(i915)) {
+ /* WaDisablePooledEuLoadBalancingFix:bxt */
+ wa_eng(wa, WA_ENG(I915_WA_MASKED,
+ FF_SLICE_CS_CHICKEN2,
+ 0,
+ GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
+ }
+
+ if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+ /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN8_GARBCNTL,
+ 0,
+ GEN9_GAPS_TSV_CREDIT_DISABLE));
+ }
+
+ if (IS_GEN9(i915) || IS_CANNONLAKE(i915)) {
+ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,cnl */
+ wa_eng(wa, WA_ENG(I915_WA_MASKED,
+ GEN7_FF_SLICE_CS_CHICKEN1,
+ 0,
+ GEN9_FFSC_PERCTX_PREEMPT_CTRL));
+ }
+
+ if (IS_ICELAKE(i915)) {
+ /* This is not an Wa. Enable for better image quality */
+ wa_eng(wa, WA_ENG(I915_WA_MASKED,
+ _3D_CHICKEN3,
+ 0,
+ _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+ /* Wa_1604302699:icl */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN10_L3_CHICKEN_MODE_REGISTER,
+ 0,
+ GEN11_I2M_WRITE_DISABLE));
+
+ /*
+ * Wa_1604223664:icl
+ * Formerly known as WaL3BankAddressHashing
+ */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN11_GLBLINVL,
+ ~GEN11_BANK_HASH_ADDR_EXCL_MASK,
+ GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+ /*
+ * Wa_1405543622:icl
+ * Formerly known as WaGAPZPriorityScheme
+ */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN8_GARBCNTL,
+ 0,
+ GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+ /*
+ * Wa_1604223664:icl
+ * Formerly known as WaL3BankAddressHashing
+ */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN8_GARBCNTL,
+ ~GEN11_HASH_CTRL_EXCL_MASK,
+ GEN11_HASH_CTRL_EXCL_BIT0));
+
+ /* WaForwardProgressSoftReset:icl */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN10_SCRATCH_LNCF2,
+ 0,
+ PMFLUSHDONE_LNICRSDROP |
+ PMFLUSH_GAPL3UNBLOCK |
+ PMFLUSHDONE_LNEBLK));
+
+ /* WaPipelineFlushCoherentLines:icl */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN8_L3SQCREG4,
+ 0,
+ GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+ /*
+ * Wa_1405733216:icl
+ * Formerly known as WaDisableCleanEvicts
+ */
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ GEN8_L3SQCREG4,
+ 0,
+ GEN11_LQSC_CLEAN_EVICT_DISABLE));
+ }
+}
+
+static void xcs_engine_wa_init(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *i915 = engine->i915;
+ struct i915_engine_workarounds *wa = &engine->wa_engine;
+
+ if (IS_KABYLAKE(i915)) {
+ /* WaKBLVECSSemaphoreWaitPoll:kbl */
+ if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
+ struct intel_engine_cs *engine;
+ unsigned int tmp;
+
+ for_each_engine(engine, i915, tmp) {
+ if (engine->id == RCS)
+ continue;
+
+ wa_eng(wa, WA_ENG(I915_WA_MASK_AND_OR,
+ RING_SEMA_WAIT_POLL(engine->mmio_base),
+ ~0,
+ 1));
+ }
+ }
+ }
+}
+
+void i915_engine_workarounds_init(struct intel_engine_cs *engine)
+{
+ struct i915_engine_workarounds *wa = &engine->wa_engine;
+
+ if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
+ return;
+
+ if (engine->id == RCS)
+ rcs_engine_wa_init(engine);
+ else
+ xcs_engine_wa_init(engine);
+
+ DRM_DEBUG_DRIVER("Initialized %u engine workarounds for %s\n",
+ wa->count, engine->name);
+}
+
+void i915_engine_workarounds_apply(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+ struct i915_engine_wa *reg;
+ unsigned int i;
+ u32 val;
+
+ if (!engine->wa_engine.count)
+ return;
+
+ for (i = 0, reg = engine->wa_engine.regs;
+ i < engine->wa_engine.count;
+ i++, reg++) {
+ switch (reg->type) {
+ case I915_WA_MASKED:
+ I915_WRITE(reg->reg, _MASKED_BIT_ENABLE(reg->val));
+printk(">wa_%s: type=%u reg=%x mask=%x val=%x\n",
+ engine->name, reg->type, i915_mmio_reg_offset(reg->reg), reg->mask, reg->val);
+ break;
+ case I915_WA_MASK_AND_OR:
+ val = I915_READ(reg->reg);
+
+ val &= ~reg->mask;
+ val |= reg->val;
+
+ I915_WRITE(reg->reg, val);
+printk(">wa_%s: type=%u reg=%x mask=%x val=%x ---> %x\n",
+ engine->name, reg->type, i915_mmio_reg_offset(reg->reg), reg->mask, reg->val, val);
+ break;
+ default:
+ MISSING_CASE(reg->type);
+ };
+ }
+
+ DRM_DEBUG_DRIVER("Applied %u engine workarounds on %s\n",
+ engine->wa_engine.count, engine->name);
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/intel_workarounds.c"
#endif
diff --git a/drivers/gpu/drm/i915/intel_workarounds.h b/drivers/gpu/drm/i915/intel_workarounds.h
index 799fb75a839c..19e1d5422c6e 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/intel_workarounds.h
@@ -7,6 +7,24 @@
#ifndef _I915_WORKAROUNDS_H_
#define _I915_WORKAROUNDS_H_
+enum i915_engine_wa_type {
+ I915_WA_MASKED,
+ I915_WA_MASK_AND_OR,
+};
+
+struct i915_engine_wa {
+ enum i915_engine_wa_type type;
+ i915_reg_t reg;
+ u32 mask;
+ u32 val;
+};
+
+struct i915_engine_workarounds {
+ unsigned int count;
+ struct i915_engine_wa *regs;
+ unsigned int __size;
+};
+
int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv);
int intel_ctx_workarounds_emit(struct i915_request *rq);
@@ -16,4 +34,7 @@ void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
+void i915_engine_workarounds_init(struct intel_engine_cs *engine);
+void i915_engine_workarounds_apply(struct intel_engine_cs *engine);
+
#endif
--
2.19.1
More information about the Intel-gfx-trybot
mailing list