[PATCH 3/4] drm/i915: Move display HW state readout to early resume phase
Imre Deak
imre.deak at intel.com
Mon Oct 8 11:27:48 UTC 2018
Signed-off-by: Imre Deak <imre.deak at intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 130 +++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_opregion.c | 2 +-
2 files changed, 67 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e7d7707a4094..2baeedbefdc7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1903,28 +1903,9 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_display_suspend(dev);
- intel_dp_mst_suspend(dev_priv);
-
- intel_runtime_pm_disable_interrupts(dev_priv);
- intel_hpd_cancel_work(dev_priv);
-
- intel_suspend_encoders(dev_priv);
-
- intel_suspend_hw(dev_priv);
-
- i915_gem_suspend_gtt_mappings(dev_priv);
-
- i915_save_state(dev_priv);
-
opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
intel_opregion_suspend(dev_priv, opregion_target_state);
- intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
-
- dev_priv->suspend_count++;
-
- intel_csr_ucode_suspend(dev_priv);
-
enable_rpm_wakeref_asserts(dev_priv);
return 0;
@@ -1950,6 +1931,26 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
disable_rpm_wakeref_asserts(dev_priv);
+ intel_dp_mst_suspend(dev_priv);
+
+ intel_runtime_pm_disable_interrupts(dev_priv);
+ intel_hpd_cancel_work(dev_priv);
+
+ intel_suspend_encoders(dev_priv);
+
+ intel_suspend_hw(dev_priv);
+
+ i915_gem_suspend_gtt_mappings(dev_priv);
+
+ i915_save_state(dev_priv);
+
+ intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
+
+ dev_priv->suspend_count++;
+
+ intel_csr_ucode_suspend(dev_priv);
+
+
i915_gem_suspend_late(dev_priv);
intel_uncore_suspend(dev_priv);
@@ -2021,53 +2022,12 @@ static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
static int i915_drm_resume(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- int ret;
disable_rpm_wakeref_asserts(dev_priv);
- intel_sanitize_gt_powersave(dev_priv);
-
- i915_gem_sanitize(dev_priv);
-
- ret = i915_ggtt_enable_hw(dev_priv);
- if (ret)
- DRM_ERROR("failed to re-enable GGTT\n");
-
- intel_csr_ucode_resume(dev_priv);
-
- i915_restore_state(dev_priv);
- intel_pps_unlock_regs_wa(dev_priv);
-
- intel_init_pch_refclk(dev_priv);
-
- /*
- * Interrupts have to be enabled before any batches are run. If not the
- * GPU will hang. i915_gem_init_hw() will initiate batches to
- * update/restore the context.
- *
- * drm_mode_config_reset() needs AUX interrupts.
- *
- * Modeset enabling in intel_modeset_init_hw() also needs working
- * interrupts.
- */
- intel_runtime_pm_enable_interrupts(dev_priv);
-
- drm_mode_config_reset(dev);
-
- i915_gem_resume(dev_priv);
-
- intel_modeset_init_hw(dev);
- intel_init_clock_gating(dev_priv);
-
- spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->display.hpd_irq_setup)
- dev_priv->display.hpd_irq_setup(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
-
- intel_dp_mst_resume(dev_priv);
-
- intel_display_readout_hw_state(dev_priv);
intel_display_resume(dev);
+ intel_opregion_resume(dev_priv);
+
drm_kms_helper_poll_enable(dev);
/*
@@ -2078,8 +2038,6 @@ static int i915_drm_resume(struct drm_device *dev)
* */
intel_hpd_init(dev_priv);
- intel_opregion_resume(dev_priv);
-
intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
intel_power_domains_enable(dev_priv);
@@ -2162,6 +2120,50 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_engines_sanitize(dev_priv);
+ intel_sanitize_gt_powersave(dev_priv);
+
+ i915_gem_sanitize(dev_priv);
+
+ ret = i915_ggtt_enable_hw(dev_priv);
+ if (ret)
+ DRM_ERROR("failed to re-enable GGTT\n");
+
+ intel_csr_ucode_resume(dev_priv);
+
+ i915_restore_state(dev_priv);
+ intel_pps_unlock_regs_wa(dev_priv);
+ intel_opregion_setup(dev_priv);
+
+ intel_init_pch_refclk(dev_priv);
+
+ /*
+ * Interrupts have to be enabled before any batches are run. If not the
+ * GPU will hang. i915_gem_init_hw() will initiate batches to
+ * update/restore the context.
+ *
+ * drm_mode_config_reset() needs AUX interrupts.
+ *
+ * Modeset enabling in intel_modeset_init_hw() also needs working
+ * interrupts.
+ */
+ intel_runtime_pm_enable_interrupts(dev_priv);
+
+ drm_mode_config_reset(dev);
+
+ i915_gem_resume(dev_priv);
+
+ intel_modeset_init_hw(dev);
+ intel_init_clock_gating(dev_priv);
+
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (dev_priv->display.hpd_irq_setup)
+ dev_priv->display.hpd_irq_setup(dev_priv);
+ spin_unlock_irq(&dev_priv->irq_lock);
+
+ intel_dp_mst_resume(dev_priv);
+
+ intel_display_readout_hw_state(dev_priv);
+
enable_rpm_wakeref_asserts(dev_priv);
return ret;
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 379e8c64a248..9120cfc69387 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -556,7 +556,7 @@ static void asle_work(struct work_struct *work)
u32 aslc_stat = 0;
u32 aslc_req;
- if (!asle)
+ if (!asle || asle->ardy != ASLE_ARDY_READY)
return;
aslc_req = asle->aslc;
--
2.13.2
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